Texas Instruments SN74LV273ADBR, SN74LV273ADGVR, SN74LV273ADW, SN74LV273APWR Datasheet

OUTPUT

SN54LV273A, SN74LV273A

OCTAL D-TYPE FLIP-FLOPS

WITH CLEAR

SCLS399A – APRIL 1998 – REVISED AUGUST 1998

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Process

D

Typical V
< 0.8 V at V

D

Typical V
> 2 V at V

D

Latch-Up Performance Exceeds 250 mA Per

(Output Ground Bounce)

OLP

CC, TA

OHV

CC

= 25°C

(Output VOH Undershoot)

, TA = 25°C

JESD 17

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic
Small-Outline (DW, NS), Shrink

SN74LV273A. . . DB, DGV, DW, NS, OR PW PACKAGE

SN54LV273A...J OR W PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

V

CC

8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK

CLR

1Q
1D
2D
2Q
3Q
3D
4D
4Q

GND

Small-Outline (DB), Thin Very Small-Outline
(DGV), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Flat (W) Packages, Chip

SN54LV273A. . . FK PACKAGE

(TOP VIEW)

Carriers (FK), and DIPs (J)

CC

description

The ’LV273A devices are octal D-type flip-flops
designed for 2-V to 5.5-V V

These devices are positive-edge-triggered
flip-flops with direct clear (CLR
at the data (D) inputs meeting the setup time

operation.

CC

) input. Information

2D
2Q
3Q
3D
4D

1D1QCLR

3212019

4
5
6
7
8

910111213

V

8Q

18

8D

17

7D

16

7Q

15

6Q

14

6D

requirements is transferred to the Q outputs on the
positive-going edge of the clock pulse. Clock
triggering occurs at a particular voltage level and

4Q

GND

CLK

5Q

5D

is not directly related to the transition time of the
positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect
at the output.

The SN54LV273A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LV273A is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLE

(each flip-flop)

INPUTS

CLK D

CLR

L X X L
H ↑ HH
H↑LL
HLXQ

OUTPUT

Q

0

Copyright  1998, Texas Instruments Incorporated

1

SN54LV273A, SN74LV273A
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR

SCLS399A – APRIL 1998 – REVISED AUGUST 1998

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

†

CLR

CLK

1D
2D
3D

4D
5D
6D
7D
8D

1
11

3
4
7

8
13
14
17
18

R

C1

1D

logic diagram (positive logic)

CLK

1D

3 4 7 8 13 14 17 18

11

1D

C1

R

2D

1D

C1

R

3D

1D

R

C1

4D

5D

1D

C1

R

1D

R

C1

12
15
16
19

2

1Q

5

2Q

6

3Q

9

4Q
5Q
6Q
7Q
8Q

6D

1D

C1

R

7D

1D

R

C1

8D

1D

C1

R

CLR

1

2 5 6 9 12 15 16 19

1Q

2Q

3Q

4Q

5Q

6Q

7Q

8Q

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

VIHHigh-level input voltage

V

VILLow-level input voltage

V

IOHHigh-level output current

IOLLow-level output current

SN54LV273A, SN74LV273A

OCTAL D-TYPE FLIP-FLOPS

WITH CLEAR

SCLS399A – APRIL 1998 – REVISED AUGUST 1998

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

(VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

(VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 3): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

†

DGV package 146°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 100°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 7 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 4)

SN54LV273A SN74LV273A

MIN MAX MIN MAX

V

V
V

∆t/∆v Input transition rise or fall rate

T

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 2 5.5 2 5.5 V

CC

VCC = 2 V 1.5 1.5

p

p

Input voltage 0 5.5 0 5.5 V

I

Output voltage 0 V

O

p

p

Operating free-air temperature –55 125 –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

VCC = 2.3 V to 2.7 V VCC × 0.7 VCC × 0.7
VCC = 3 V to 3.6 V VCC × 0.7 VCC × 0.7
VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7
VCC = 2 V 0.5 0.5
VCC = 2.3 V to 2.7 V VCC × 0.3 VCC × 0.3
VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3
VCC = 4.5 V to 5.5 V VCC × 0.3 VCC × 0.3

CC

VCC = 2 V –50 –50 µA
VCC = 2.3 V to 2.7 V –2 –2
VCC = 3 V to 3.6 V –6 –6
VCC = 4.5 V to 5.5 V –12 –12
VCC = 2 V 50 50 µA
VCC = 2.3 V to 2.7 V 2 2
VCC = 3 V to 3.6 V 6 6
VCC = 4.5 V to 5.5 V 12 12
VCC = 2.3 V to 2.7 V 0 200 0 200
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V 0 20 0 20

, literature number SCBA004.

0 100 0 100

0 V

CC

V

mA

mA

ns/V

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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