Texas Instruments SN74LV245ADBLE, SN74LV245ADBR, SN74LV245ADGVR, SN74LV245ADW, SN74LV245ADWR Datasheet
...
OPERATION
SN54LV245A, SN74LV245A
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCLS382C – SEPTEMBER 1997 – REVISED JUNE 1998
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Typical V
< 0.8 V at V
D
Typical V
> 2 V at V
D
Latch-Up Performance Exceeds 250 mA Per
(Output Ground Bounce)
OLP
, TA = 25°C
CC
(Output VOH Undershoot)
OHV
, TA = 25°C
CC
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (DW, NS), Shrink
Small-Outline (DB), Thin Very Small-Outline
(DGV), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Flat (W) Packages, Chip
Carriers (FK), and DIPs (J)
description
These octal bus transceivers are designed for 2-V
to 5.5-V V
The ’LV245A devices are designed for
asynchronous communication between data
buses. The device transmits data from the A bus
to the B bus or from the B bus to the A bus,
depending on the logic level at the
direction-control (DIR) input. The output-enable
(OE
) input can be used to disable the device so
the buses are effectively isolated.
operation.
CC
SN74LV245A. . . DB, DGV, DW , NS, OR PW PACKAGE
SN54LV245A...J OR W PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
GND
B8
20
19
18
17
16
15
14
13
12
11
V
B7
CC
V
OE
B1
B2
B3
B4
B5
B6
B7
B8
OE
18
17
16
15
14
B6
CC
B1
B2
B3
B4
B5
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
SN54LV245A. . . FK PACKAGE
A3
A4
A5
A6
A7
(TOP VIEW)
A2A1DIR
3212019
4
5
6
7
8
910111213
A8
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54LV245A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LV245A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OE DIR
L L B data to A bus
L H A data to B bus
H X Isolation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Copyright 1998, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54LV245A, SN74LV245A
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCLS382C – SEPTEMBER 1997 – REVISED JUNE 1998
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
OE
DIR
A1
A2
A3
A4
A5
A6
A7
A8
19
1
2
3
4
5
6
7
8
9
G3
3 EN1 [BA]
3 EN2 [AB]
1
2
logic diagram (positive logic)
1
DIR
18
17
16
15
14
13
12
11
B1
B2
B3
B4
B5
B6
B7
B8
A1
19
OE
2
18
B1
To Seven Other Channels
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV245A, SN74LV245A
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCLS382C – SEPTEMBER 1997 – REVISED JUNE 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Output voltage range applied in the high or low state, V
Output voltage range applied in high-impedance or power-off state, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
: Except I/O ports (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
I/O ports (see Notes 1 and 2) –0.5 V to V
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . .
O
(VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
(VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 3): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
(see Note 1) –0.5 V to 7 V. . . . . . .
O
DGV package 146°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 100°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54LV245A, SN74LV245A
UNIT
VIHHigh-level input voltage
V
VILLow-level input voltage
V
VOOutput voltage
V
IOHHigh-level output current
IOLLow-level output current
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCLS382C – SEPTEMBER 1997 – REVISED JUNE 1998
recommended operating conditions (see Note 4)
SN54LV245A SN74LV245A
MIN MAX MIN MAX
V
V
∆t/∆v Input transition rise or fall rate
T
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2 5.5 2 5.5 V
CC
VCC = 2 V 1.5 1.5
p
p
Input voltage 0 5.5 0 5.5 V
I
p
p
p
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
VCC = 2.3 V to 2.7 V VCC× 0.7 VCC× 0.7
VCC = 3 V to 3.6 V VCC× 0.7 VCC× 0.7
VCC = 4.5 V to 5.5 V VCC× 0.7 VCC× 0.7
VCC = 2 V 0.5 0.5
VCC = 2.3 V to 2.7 V VCC× 0.3 VCC× 0.3
VCC = 3 V to 3.6 V VCC× 0.3 VCC× 0.3
VCC = 4.5 V to 5.5 V VCC× 0.3 VCC× 0.3
High or low state 0 V
3-state 0 5.5 0 5.5
VCC = 2 V –50 –50 µA
VCC = 2.3 V to 2.7 V –2 –2
VCC = 3 V to 3.6 V –8 –8
VCC = 4.5 V to 5.5 V –16 –16
VCC = 2 V 50 50 µA
VCC = 2.3 V to 2.7 V 2 2
VCC = 3 V to 3.6 V 8 8
VCC = 4.5 V to 5.5 V 16 16
VCC = 2.3 V to 2.7 V 0 200 0 200
VCC = 3 V to 3.6 V 0 100 0 100
VCC = 4.5 V to 5.5 V 0 20 0 20
, literature number SCBA004.
CC
0 V
CC
mA
mA
ns/V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
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PARAMETER
TEST CONDITIONS
V
UNIT
V
V
V
V
CiControl inputs
V
V
GND
pF
CioA or B port
V
V
or GND
pF
PARAMETER
UNIT
C
F
SN54LV245A, SN74LV245A
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCLS382C – SEPTEMBER 1997 – REVISED JUNE 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV245A SN74LV245A
MIN TYP MAX MIN TYP MAX
p
p
I
I
I
I
OH
OL
I
OZ
CC
off
CC
IOH = –50 µA 2 V to 5.5 V VCC–0.1 VCC–0.1
IOH = –2 mA 2.3 V 2 2
IOH = –8 mA 3 V 2.48 2.48
IOH = –16 mA 4.5 V 3.8 3.8
IOL = 50 µA 2 V to 5.5 V 0.1 0.1
IOL = 2 mA 2.3 V 0.4 0.4
IOL = 8 mA 3 V 0.44 0.44
IOL = 16 mA 4.5 V 0.55 0.55
VI = VCC or GND 5.5 V ±1 ±1 µ A
VO = VCC or GND 5.5 V ±5 ±5 µ A
VI = VCC or GND, IO = 0 5.5 V 20 20 µA
VI or VO = 0 to 5.5 V 0 V 5 5 µA
p
p
=
or
I
CC
=
CC
O
3.3 V 2.4 2.4
5 V 2.4 2.4
3.3 V 5.4 5.4
5 V 5.4 5.4
switching characteristics over recommended operating free-air temperature range,
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
V
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
tpd* A or B B or A 8.3 13 1 15 1 15
ten*
t
*
dis
t
pd
t
en
t
dis
†
t
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
Skew between any two outputs of the same package switching in the same direction
OE
OE
A or B B or A 1 1.2 15.9 1 18 1 18
OE
OE
A or B
A or B 11.8 18.1 1 20 1 20
A or B
A or B
CL = 15 pF
= 50 p
L
TA = 25°C SN54LV245A SN74LV245A
MIN TYP MAX MIN MAX MIN MAX
11.8 19.9 1 22 1 22
14.1 22.7 1 26 1 26
17.6 23.1 1 25 1 25
2 2
ns
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54LV245A, SN74LV245A
PARAMETER
UNIT
C
F
PARAMETER
UNIT
C
F
PARAMETER
UNIT
C
d
Power dissi ation ca acitance
Out uts enabled
C
L
MHz
F
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCLS382C – SEPTEMBER 1997 – REVISED JUNE 1998
switching characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
tpd* A or B B or A 5.9 8.4 1 10 1 10
ten*
t
*
dis
t
pd
t
en
t
dis
†
t
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
Skew between any two outputs of the same package switching in the same direction
OE
OE
A or B B or A 7.9 11.9 1 13.5 1 13.5
OE
OE
A or B
A or B 9.6 16.5 1 19.5 1 19.5
A or B
A or B
CL = 15 pF
= 50 p
L
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
tpd* A or B B or A 4.3 5.5 1 6.5 1 6.5
ten*
t
*
dis
t
pd
t
en
t
dis
†
t
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
Skew between any two outputs of the same package switching in the same direction
OE
OE
A or B B or A 5.6 7.5 1 8.5 1 8.5
OE
OE
A or B
A or B 7.8 12.8 1 14.7 1 14.2
A or B
A or B
CL = 15 pF
= 50 p
L
TA = 25°C SN54LV245A SN74LV245A
MIN TYP MAX MIN MAX MIN MAX
8.2 13.2 1 15.5 1 15.5
9.9 16.7 1 19 1 19
13.9 19.8 1 22 1 22
1.5 1.5
TA = 25°C SN54LV245A SN74LV245A
MIN TYP MAX MIN MAX MIN MAX
5.7 8.5 1 10.6 1 10
7 10.6 1 12 1 12
10.9 14.7 1 16 1 16
1 1
ns
ns
ns
ns
noise characteristics, V
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
NOTE 5: Characteristics are for surface-mount packages only.
Quiet output, maximum dynamic V
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage 2.31 V
Low-level dynamic input voltage 0.99 V
= 3.3 V, CL = 50 pF, TA = 25°C (see Note 5)
CC
OL
OL
OH
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS V
p
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
p
p
SN74LV245A
MIN TYP MAX
0.45 V
–0.45 V
2.94 V
TYP UNIT
CC
p
p
= 50 F,f = 10
3.3 V 20
5 V 25
p
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
(see Note A)
SN54LV245A, SN74LV245A
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCLS382C – SEPTEMBER 1997 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
V
Test
Point
C
L
From Output
Under Test
(see Note A)
C
L
RL = 1 kΩ
S1
CC
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
Open
V
CC
GND
V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
t
w
Input
Input
In-Phase
Output
Out-of-Phase
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. t
F. t
G. t
50% V
CC
VOLTAGE WAVEFORMS
PULSE DURATION
50% V
CC
t
PLH
50% V
CC
t
PHL
50% V
CC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
PLZ
PZL
PHL
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PLH
3-STATE AND OPEN-DRAIN OUTPUTS
50% V
50% V
CC
dis
t
PHL
50% V
t
PLH
50% V
.
LOAD CIRCUIT FOR
V
CC
CC
0 V
V
CC
0 V
V
OH
CC
V
OL
V
OH
CC
V
OL
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at V
(see Note B)
Waveform 2
(see Note B)
CC
Output
S1 at GND
50% V
CC
t
CC
CC
h
50% V
50% V
CC
VOL + 0.3 V
VOH – 0.3 V
t
su
50% V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
50% V
CC
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
t
PLZ
50% V
t
PHZ
50% V
CC
V
CC
0 V
V
CC
0 V
V
CC
0 V
≈ V
V
OL
V
OH
≈ 0 V
CC
Figure 1. Load Circuit and Voltage Waveforms
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7
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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performed, except those mandated by government requirements.
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Copyright 1998, Texas Instruments Incorporated
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