Texas Instruments SN74LV175AD, SN74LV175ADBR, SN74LV175ADGVR, SN74LV175ADR, SN74LV175APWR Datasheet
SN54LV175A, SN74LV175A
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS400B – APRIL 1998 – REVISED OCTOBER 1998
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Typical V
< 0.8 V at V
D
Typical V
> 2 V at V
D
Contain Four Flip-Flops With Double-Rail
(Output Ground Bounce)
OLP
= 3.3 V, TA = 25°C
CC
(Output VOH Undershoot)
OHV
= 3.3 V, TA = 25°C
CC
Outputs
D
Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)
SN74LV175A. . . D, DB, DGV, NS, OR PW PACKAGE
SN54LV175A...J OR W PACKAGE
(TOP VIEW)
CLR
1
1Q
2
1Q
3
1D
4
2D
5
2Q
6
2Q
7
GND
SN54LV175A. . . FK PACKAGE
1Q
1D
NC
2D
2Q
8
(TOP VIEW)
1Q
CLR
3212019
4
5
6
7
8
910111213
NC
16
15
14
13
12
11
10
9
V
CC
V
4Q
4Q
4D
3D
3Q
3Q
CLK
4Q
18
17
16
15
14
CC
4Q
4D
NC
3D
3Q
description
The ’LV175A devices are quadruple D-type
flip-flops designed for 2-V to 5.5-V V
These devices have a direct clear (CLR
CC
2Q
GND
NC – No internal connection
operation.
) input and feature complementary outputs from each flip-flop.
NC
CLK
3Q
Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the
positive-going edge of the clock (CLK) pulse.
Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the
positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.
The SN54LV175A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LV175A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
CLR CLK D Q Q
L X X L H
H ↑ HHL
H↑LLH
HLXQ
OUTPUTS
Q
0
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1998, Texas Instruments Incorporated
1
SN54LV175A, SN74LV175A
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS400B – APRIL 1998 – REVISED OCTOBER 1998
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
†
CLR
CLK
1D
2D
3D
4D
1
9
4
5
12
13
R
C1
1D
logic diagram (positive logic)
1
CLR
9
CLK
10
11
15
14
2
1Q
3
1Q
7
2Q
6
2Q
3Q
3Q
4Q
4Q
4
1D
To Three Other Channels
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
1D
R
C1
2
1Q
3
1Q
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
VIHHigh-level input voltage
V
VILLow-level input voltage
V
IOHHigh-level output current
IOLLow-level output current
SN54LV175A, SN74LV175A
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS400B – APRIL 1998 – REVISED OCTOBER 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
(VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 3): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
†
DB package 131°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 180°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 11 1° C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 149°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 4)
SN54LV175A SN74LV175A
MIN MAX MIN MAX
V
V
V
∆t/∆v Input transition rise or fall rate
T
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2 5.5 2 5.5 V
CC
VCC = 2 V 1.5 1.5
p
p
Input voltage 0 5.5 0 5.5 V
I
Output voltage 0 V
O
p
p
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
VCC = 2.3 V to 2.7 V VCC× 0.7 VCC× 0.7
VCC = 3 V to 3.6 V VCC× 0.7 VCC× 0.7
VCC = 4.5 V to 5.5 V VCC× 0.7 VCC× 0.7
VCC = 2 V 0.5 0.5
VCC = 2.3 V to 2.7 V VCC× 0.3 VCC× 0.3
VCC = 3 V to 3.6 V VCC× 0.3 VCC× 0.3
VCC = 4.5 V to 5.5 V VCC× 0.3 VCC× 0.3
CC
VCC = 2 V –50 –50 µA
VCC = 2.3 V to 2.7 V –2 –2
VCC = 3 V to 3.6 V –6 –6
VCC = 4.5 V to 5.5 V –12 –12
VCC = 2 V 50 50 µA
VCC = 2.3 V to 2.7 V 2 2
VCC = 3 V to 3.6 V 6 6
VCC = 4.5 V to 5.5 V 12 12
VCC = 2.3 V to 2.7 V 0 200 0 200
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V 0 20 0 20
, literature number SCBA004.
0 100 0 100
0 V
CC
V
mA
mA
ns/V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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