Texas Instruments SN74LV174AD, SN74LV174ADBR, SN74LV174ADGVR, SN74LV174ADR, SN74LV174APWR Datasheet

SN54LV174A, SN74LV174A

HEX D-TYPE FLIP-FLOPS

WITH CLEAR

SCLS401B – APRIL 1998 – REVISED JUL Y 1998

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Process

D

Typical V
< 0.8 V at V

D

Typical V

(Output Ground Bounce)

OLP

, TA = 25°C

CC

(Output VOH Undershoot)

OHV

> 2 V at VCC, TA = 25°C

D

Latch-Up Performance Exceeds 250 mA
Per JESD 17

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and

SN74LV174A. . . D, DB, DGV, NS, OR PW PACKAGE

SN54LV174A...J OR W PACKAGE

(TOP VIEW)

CLR

1

1Q

2

1D

3

2D

4

2Q

5

3D

6

3Q

7

GND

SN54LV174A. . . FK PACKAGE

8

(TOP VIEW)

16
15
14
13
12
11
10

V

CC

6Q
6D
5D
5Q
4D
4Q
CLK

9

Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers

1Q

CLR

NC

V

CC

6Q

(FK), and DIPs (J)

description

The ’LV174A devices are hex D-type flip-flops
designed for 2-V to 5.5-V VCC operation.

These devices are monolithic positive-edge-

1D
2D

NC

2Q
3D

3212019

4
5
6
7
8

910111213

18
17
16
15
14

6D
5D
NC
5Q
4D

triggered flip-flops with a direct clear (CLR) input.
Information at the data (D) inputs meeting the
setup time requirements is transferred to the
outputs on the positive-going edge of the clock

3Q

GND

NC – No internal connection

NC

CLK

4Q

pulse. Clock triggering occurs at a particular
voltage level and is not directly related to the
transition time of the positive-going edge of the clock pulse. When the clock (CLK) input is at either the high or
low level, the D-input signal has no effect at the output.

The SN54LV174A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LV174A is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

INPUTS

CLR CLK D

L X X L
H ↑ HH
H ↑ LL
H L X Q

OUTPUT

Q

0

Copyright  1998, Texas Instruments Incorporated

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

SN54LV174A, SN74LV174A
HEX D-TYPE FLIP-FLOPS
WITH CLEAR

SCLS401B – APRIL 1998 – REVISED JUL Y 1998

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.

†

1

CLR

9

CLK C1

3

1D

4

2D

6

3D

11

4D

13

5D

14

6D

R

1D

logic diagram (positive logic)

1

CLR

9

CLK

3

1D

1D

C1

R

10
12
15

2

1Q

5

2Q

7

3Q
4Q
5Q
6Q

2

1Q

To Five Other Channels

Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

Output voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through V

Package thermal impedance, θJA (see Note 3): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 7 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

DB package 131°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 180°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 11 1°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 149°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

‡

2

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UNIT

VIHHigh-level input voltage

V

VILLow-level input voltage

V

IOHHigh-level output current

IOLLow-level output current

PARAMETER

TEST CONDITIONS

V

UNIT

V

V

V

V

SN54LV174A, SN74LV174A

HEX D-TYPE FLIP-FLOPS

WITH CLEAR

SCLS401B – APRIL 1998 – REVISED JUL Y 1998

recommended operating conditions (see Note 4)

SN54LV174A SN74LV174A

MIN MAX MIN MAX

V

V
V

∆t/∆v Input transition rise or fall rate

T

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 2 5.5 2 5.5 V

CC

VCC = 2 V 1.5 1.5

p

p

Input voltage 0 5.5 0 5.5 V

I

Output voltage 0 V

O

p

p

Operating free-air temperature –55 125 –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

VCC = 2.3 V to 2.7 V VCC × 0.7 VCC × 0.7
VCC = 3 V to 3.6 V VCC × 0.7 VCC × 0.7
VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7
VCC = 2 V 0.5 0.5
VCC = 2.3 V to 2.7 V VCC × 0.3 VCC × 0.3
VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3
VCC = 4.5 V to 5.5 V VCC × 0.3 VCC × 0.3

CC

VCC = 2 V –50 –50 µA
VCC = 2.3 V to 2.7 V –2 –2
VCC = 3 V to 3.6 V –6 –6
VCC = 4.5 V to 5.5 V –12 –12
VCC = 2 V 50 50 µA
VCC = 2.3 V to 2.7 V 2 2
VCC = 3 V to 3.6 V 6 6
VCC = 4.5 V to 5.5 V 12 12
VCC = 2.3 V to 2.7 V 0 200 0 200
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V 0 20 0 20

, literature number SCBA004.

0 100 0 100

0 V

CC

V

mA

mA

ns/V

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

SN54LV174A SN74LV174A

MIN TYP MAX MIN TYP MAX

IOH = –50 µA 2 V to 5.5 V VCC–0.1 VCC–0.1

OH

OL

I

I

I

CC

I

off

C

i

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

IOH = –2 mA 2.3 V 2 2
IOH = –6 mA 3 V 2.48 2.48
IOH = –12 mA 4.5 V 3.8 3.8
IOL = 50 µA 2 V to 5.5 V 0.1 0.1
IOL = 2 mA 2.3 V 0.4 0.4
IOL = 6 mA 3 V 0.44 0.44
IOL = 12 mA 4.5 V 0.55 0.55
VI = VCC or GND 5.5 V ±1 ±1 µA
VI = VCC or GND, IO = 0 5.5 V 20 20 µA
VI or VO = 0 to 5.5 V 0 V 5 5 µA
VI = VCC or GND 3.3 V 1.7 1.7 pF

CC

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