Datasheet SN74LV174AD, SN74LV174ADBR, SN74LV174ADGVR, SN74LV174ADR, SN74LV174APWR Datasheet (Texas Instruments)
SN54LV174A, SN74LV174A
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS401B – APRIL 1998 – REVISED JUL Y 1998
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Typical V
< 0.8 V at V
D
Typical V
(Output Ground Bounce)
OLP
, TA = 25°C
CC
(Output VOH Undershoot)
OHV
> 2 V at VCC, TA = 25°C
D
Latch-Up Performance Exceeds 250 mA
Per JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
SN74LV174A. . . D, DB, DGV, NS, OR PW PACKAGE
SN54LV174A...J OR W PACKAGE
(TOP VIEW)
CLR
1
1Q
2
1D
3
2D
4
2Q
5
3D
6
3Q
7
GND
SN54LV174A. . . FK PACKAGE
8
(TOP VIEW)
16
15
14
13
12
11
10
V
CC
6Q
6D
5D
5Q
4D
4Q
CLK
9
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers
1Q
CLR
NC
V
CC
6Q
(FK), and DIPs (J)
description
The ’LV174A devices are hex D-type flip-flops
designed for 2-V to 5.5-V VCC operation.
These devices are monolithic positive-edge-
1D
2D
NC
2Q
3D
3212019
4
5
6
7
8
910111213
18
17
16
15
14
6D
5D
NC
5Q
4D
triggered flip-flops with a direct clear (CLR) input.
Information at the data (D) inputs meeting the
setup time requirements is transferred to the
outputs on the positive-going edge of the clock
3Q
GND
NC – No internal connection
NC
CLK
4Q
pulse. Clock triggering occurs at a particular
voltage level and is not directly related to the
transition time of the positive-going edge of the clock pulse. When the clock (CLK) input is at either the high or
low level, the D-input signal has no effect at the output.
The SN54LV174A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LV174A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
INPUTS
CLR CLK D
L X X L
H ↑ HH
H ↑ LL
H L X Q
OUTPUT
Q
0
Copyright 1998, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54LV174A, SN74LV174A
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS401B – APRIL 1998 – REVISED JUL Y 1998
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
†
1
CLR
9
CLK C1
3
1D
4
2D
6
3D
11
4D
13
5D
14
6D
R
1D
logic diagram (positive logic)
1
CLR
9
CLK
3
1D
1D
C1
R
10
12
15
2
1Q
5
2Q
7
3Q
4Q
5Q
6Q
2
1Q
To Five Other Channels
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
Output voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
Package thermal impedance, θJA (see Note 3): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
DB package 131°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 180°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 11 1°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 149°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
‡
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
VIHHigh-level input voltage
V
VILLow-level input voltage
V
IOHHigh-level output current
IOLLow-level output current
PARAMETER
TEST CONDITIONS
V
UNIT
V
V
V
V
SN54LV174A, SN74LV174A
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS401B – APRIL 1998 – REVISED JUL Y 1998
recommended operating conditions (see Note 4)
SN54LV174A SN74LV174A
MIN MAX MIN MAX
V
V
V
∆t/∆v Input transition rise or fall rate
T
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2 5.5 2 5.5 V
CC
VCC = 2 V 1.5 1.5
p
p
Input voltage 0 5.5 0 5.5 V
I
Output voltage 0 V
O
p
p
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
VCC = 2.3 V to 2.7 V VCC × 0.7 VCC × 0.7
VCC = 3 V to 3.6 V VCC × 0.7 VCC × 0.7
VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7
VCC = 2 V 0.5 0.5
VCC = 2.3 V to 2.7 V VCC × 0.3 VCC × 0.3
VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3
VCC = 4.5 V to 5.5 V VCC × 0.3 VCC × 0.3
CC
VCC = 2 V –50 –50 µA
VCC = 2.3 V to 2.7 V –2 –2
VCC = 3 V to 3.6 V –6 –6
VCC = 4.5 V to 5.5 V –12 –12
VCC = 2 V 50 50 µA
VCC = 2.3 V to 2.7 V 2 2
VCC = 3 V to 3.6 V 6 6
VCC = 4.5 V to 5.5 V 12 12
VCC = 2.3 V to 2.7 V 0 200 0 200
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V 0 20 0 20
, literature number SCBA004.
0 100 0 100
0 V
CC
V
mA
mA
ns/V
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV174A SN74LV174A
MIN TYP MAX MIN TYP MAX
IOH = –50 µA 2 V to 5.5 V VCC–0.1 VCC–0.1
OH
OL
I
I
I
CC
I
off
C
i
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
IOH = –2 mA 2.3 V 2 2
IOH = –6 mA 3 V 2.48 2.48
IOH = –12 mA 4.5 V 3.8 3.8
IOL = 50 µA 2 V to 5.5 V 0.1 0.1
IOL = 2 mA 2.3 V 0.4 0.4
IOL = 6 mA 3 V 0.44 0.44
IOL = 12 mA 4.5 V 0.55 0.55
VI = VCC or GND 5.5 V ±1 ±1 µA
VI = VCC or GND, IO = 0 5.5 V 20 20 µA
VI or VO = 0 to 5.5 V 0 V 5 5 µA
VI = VCC or GND 3.3 V 1.7 1.7 pF
CC
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54LV174A, SN74LV174A
UNIT
twPulse duration
ns
t
S
CLK↑
ns
UNIT
twPulse duration
ns
t
S
CLK↑
ns
UNIT
twPulse duration
ns
t
S
CLK↑
ns
PARAMETER
UNIT
f
MH
t
d
Q
C
15 pF
ns
t
d
Q
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS401B – APRIL 1998 – REVISED JUL Y 1998
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54LV174A SN74LV174A
MIN TYP MAX MIN MAX MIN MAX
CLR low 6 6.5 6.5
CLK high or low 7 7 7
su
t
h
etup time before
Hold time, data after CLK↑ –0.5 0 0 ns
Data 8.5 9.5 9.5
CLR inactive 4 4 4
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54LV174A SN74LV174A
MIN TYP MAX MIN MAX MIN MAX
CLR low 5 5 5
CLK high or low 5 5 5
su
t
h
etup time before
Hold time, data after CLK↑ 0 0 0 ns
Data 5 6 6
CLR inactive 3 3 3
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54LV174A SN74LV174A
MIN TYP MAX MIN MAX MIN MAX
CLR low 5 5 5
CLK high or low 5 5 5
su
t
h
etup time before
Hold time, data after CLK↑ 0.5 0.5 0.5 ns
Data 4.5 4.5 4.5
CLR inactive 2.5 2.5 2.5
= 2.5 V± 0.2 V
CC
= 3.3 V± 0.3 V
CC
= 5 V ± 0.5 V
CC
switching characteristics over recommended operating free-air temperature range,
V
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
max
*
p
p
†
t
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
Skew between any two outputs of the same package switching in the same direction
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
CLR
CLK
CLR
CLK
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CL = 15 pF* 55 115 50 50
CL = 50 pF 45 90 40 40
p
=
L
CL = 50 pF
TA = 25°C SN54LV174A SN74LV174A
MIN TYP MAX MIN MAX MIN MAX
6.3 17.3 1 19.5 1 19.5
8.4 17.1 1 19 1 19
8.2 21.9 1 23.5 1 23.5
10.8 20.6 1 23 1 23
2 2
z
ns
PARAMETER
UNIT
f
MH
t
d
Q
C
pF
ns
t
d
Q
PARAMETER
UNIT
f
MH
t
d
Q
C
15 pF
ns
t
d
Q
PARAMETER
UNIT
C
d
Power dissi ation ca acitance
C
L
MHz
F
SN54LV174A, SN74LV174A
HEX D-TYPE FLIP-FLOPS
SCLS401B – APRIL 1998 – REVISED JUL Y 1998
switching characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
max
*
p
p
†
t
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
Skew between any two outputs of the same package switching in the same direction
CLR
CLK
CLR
CLK
CL = 15 pF* 95 170 80 80
CL = 50 pF 55 130 50 50
p
= 15
L
CL = 50 pF
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
max
*
p
p
†
t
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
Skew between any two outputs of the same package switching in the same direction
CLR
CLK
CLR
CLK
CL = 15 pF* 130 240 110 110
CL = 50 pF 90 180 80 80
p
=
L
CL = 50 pF
TA = 25°C SN54LV174A SN74LV174A
MIN TYP MAX MIN MAX MIN MAX
4.5 11.4 1 13.5 1 13.5
5.8 11 1 13 1 13
6 14.9 1 17 1 17
7.5 14.5 1 16.5 1 16.5
1.5 1.5
TA = 25°C SN54LV174A SN74LV174A
MIN TYP MAX MIN MAX MIN MAX
3 7.6 1 9 1 9
4.1 7.2 1 8.5 1 8.5
4.2 9.6 1 11 1 11
5.5 9.2 1 10.5 1 10.5
1 1
WITH CLEAR
z
ns
z
ns
noise characteristics, V
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
NOTE 5: Characteristics are for surface-mount packages only.
Quiet output, maximum dynamic V
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage 2.31 V
Low-level dynamic input voltage 0.99 V
= 3.3 V, C
CC
= 50 pF, TA = 25°C (see Note 5)
L
OL
OL
OH
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS V
p
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
p
p
p
= 50 F,f = 10
SN74LV174A
MIN TYP MAX
0.34 0.8 V
–0.3 –0.8 V
3.02 V
TYP UNIT
CC
3.3 V 14
5 V 15.1
p
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54LV174A, SN74LV174A
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS401B – APRIL 1998 – REVISED JUL Y 1998
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
(see Note A)
Test
Point
C
L
From Output
Under Test
(see Note A)
V
RL = 1 kΩ
C
L
S1
CC
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
Open
V
CC
GND
V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
t
w
Input
Input
In-Phase
Output
Out-of-Phase
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. t
F. t
G. t
50% V
CC
VOLTAGE WAVEFORMS
PULSE DURATION
50% V
CC
t
PLH
50% V
CC
t
PHL
50% V
CC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
PLZ
PZL
PHL
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PLH
3-STATE AND OPEN-DRAIN OUTPUTS
50% V
50% V
dis
CC
t
PHL
50% V
t
PLH
50% V
.
LOAD CIRCUIT FOR
V
CC
CC
0 V
V
CC
0 V
V
OH
CC
V
OL
V
OH
CC
V
OL
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at V
(see Note B)
Waveform 2
(see Note B)
CC
Output
S1 at GND
50% V
CC
t
CC
CC
h
50% V
50% V
VOL + 0.3 V
VOH – 0.3 V
CC
CC
t
su
50% V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
50% V
CC
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
t
PLZ
50% V
t
PHZ
50% V
V
CC
0 V
V
CC
0 V
V
CC
0 V
≈ V
V
OL
V
OH
≈ 0 V
CC
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICA TIONS USING SEMICONDUCTOR PRODUCTS MA Y INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
Loading...