Texas Instruments SN74LV165AD, SN74LV165ADBR, SN74LV165ADGVR, SN74LV165ADR, SN74LV165APWR Datasheet

OPERATION

SN54LV165A, SN74LV165A

PARALLEL-LOAD 8-BIT SHIFT REGISTERS

SCLS402B – APRIL 1998 – REVISED JUL Y 1998

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Process

D

Typical V
< 0.8 V at V

D

Typical V
< 2 V at V

D

Latch-Up Performance Exceeds 250 mA Per

(Output Ground Bounce)

OLP

, TA = 25°C

CC

(Output VOH Undershoot)

OHV

, TA = 25°C

CC

JESD 17

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and

SN74LV165A. . . D, DB, DGV, NS, OR PW PACKAGE

SN54LV165A...J OR W PACKAGE

(TOP VIEW)

SH/LD

GND

SN54LV165A. . . FK PACKAGE

CLK

Q

E

F
G
H

H

1
2
3
4
5
6
7
8

(TOP VIEW)

16
15
14
13
12
11
10

9

V

CC

CLK INH
D
C
B
A
SER
Q

H

Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)

description

4

The ’LV165A devices are parallel-load, 8-bit shift
registers designed for 2-V to 5.5-V V

operation.

CC

When the device is clocked, data is shifted toward
the serial output Q

. Parallel-in access to each

H

stage is provided by eight individual direct data
inputs that are enabled by a low level at the
shift/load (SH/LD

) input. The ’LV165A devices
feature a clock inhibit function and a
complemented serial output Q

.

H

Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD

E

5

F

6

NC

7

G

8

H

NC – No internal connection

CLK

3212019

910111213

H

Q

SH/LD

NC

NC

GND

CC

V

CLK INH

D

18
17

C

16

NC

15

B

14

A

H

Q

SER

is held high and clock
inhibit (CLK INH) is held low. The functions of the CLK and CLK INH inputs are interchangeable. Since a low
CLK input and a low-to-high transition of CLK INH accomplishes clocking, CLK INH should be changed to the
high level only while CLK is high. Parallel loading is inhibited when SH/LD
the register are enabled while SH/LD

is held low, independently of the levels of CLK, CLK INH, or SER.

is held high. The parallel inputs to

The SN54L V165A is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LV165A is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

SH/LD CLK CLK INH

L X X Parallel load
H HX Q
HXH Q
HL↑ Shift
H ↑ L Shift

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

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0

Copyright  1998, Texas Instruments Incorporated

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SN54LV165A, SN74LV165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS

SCLS402B – APRIL 1998 – REVISED JUL Y 1998

logic diagram (positive logic)

ABCDEFGH

11 12 13 14 3 4 5 6

SH/LD

1

CLK

SER

15

2

10

S
1D

R

C1

S
1D

R

C1

S
1D

R

C1

CLK INH

Pin numbers shown are for the D, DB, DGV , J, NS, PW, and W packages.

typical shift, load, and inhibit sequences

CLK

CLK INH

SER

SH/LD

A

L

H

S
1D

R

C1

S
1D

R

C1

S
1D

R

C1

S
1D

R

C1

S
1D

R

C1

9

Q

H

7

Q

H

Data

Inputs

B

C

D

E

F

G

H

Q

H

Q

H

L

H

L

H

L

H

H

L

H

H

L

L

H

L

H

L

H

L

H

L

H

L

H

Serial ShiftInhibit

Load

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

VIHHigh-level input voltage

V

VILLow-level input voltage

V

IOHHigh-level output current

IOLLow-level output current

SN54LV165A, SN74LV165A

PARALLEL-LOAD 8-BIT SHIFT REGISTERS

SCLS402B – APRIL 1998 – REVISED JUL Y 1998

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

(VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

(VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 3): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

†

DB package 131°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 180°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 11 1° C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 149°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 7 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 4)

SN54LV165A SN74LV165A

MIN MAX MIN MAX

V

V
V

∆t/∆v Input transition rise or fall rate

T

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 2 5.5 2 5.5 V

CC

VCC = 2 V 1.5 1.5

p

p

Input voltage 0 5.5 0 5.5 V

I

Output voltage 0 V

O

p

p

Operating free-air temperature –55 125 –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

VCC = 2.3 V to 2.7 V VCC × 0.7 VCC × 0.7
VCC = 3 V to 3.6 V VCC × 0.7 VCC × 0.7
VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7
VCC = 2 V 0.5 0.5
VCC = 2.3 V to 2.7 V VCC × 0.3 VCC × 0.3
VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3
VCC = 4.5 V to 5.5 V VCC × 0.3 VCC × 0.3

CC

VCC = 2 V –50 –50 µ A
VCC = 2.3 V to 2.7 V –2 –2
VCC = 3 V to 3.6 V –6 –6
VCC = 4.5 V to 5.5 V –12 –12
VCC = 2 V 50 50 µA
VCC = 2.3 V to 2.7 V 2 2
VCC = 3 V to 3.6 V 6 6
VCC = 4.5 V to 5.5 V 12 12
VCC = 2.3 V to 2.7 V 0 200 0 200
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V 0 20 0 20

, literature number SCBA004.

0 100 0 100

0 V

CC

V

mA

mA

ns/V

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

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