Texas Instruments SN74LV164AD, SN74LV164ADBR, SN74LV164ADGVR, SN74LV164ADR, SN74LV164APWR Datasheet
SN54LV164A, SN74LV164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403B – APRIL 1998 – REVISED JUNE 1998
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Typical V
< 0.8 V at V
D
Typical V
(Output Ground Bounce)
OLP
, TA = 25°C
CC
(Output VOH Undershoot)
OHV
> 2 V at VCC, TA = 25°C
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
SN74LV164A. . . D, DB, DGV, NS, OR PW PACKAGE
SN54LV164A...J OR W PACKAGE
(TOP VIEW)
14
13
12
11
10
V
CC
Q
H
Q
G
Q
F
Q
E
CLR
9
CLK
8
Q
Q
Q
Q
GND
A
1
B
2
3
A
4
B
5
C
6
D
7
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
SN54LV164A. . . FK PACKAGE
(TOP VIEW)
BANC
V
CC
H
Q
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)
description
The ’LV164A devices are 8-bit parallel-out serial
shift registers designed for 2-V to 5.5-V V
operation.
These devices feature AND-gated serial (A and B)
inputs and an asynchronous clear (CLR) input.
The gated serial inputs permit complete control
CC
Q
NC
Q
NC
Q
NC – No internal connection
3212019
4
A
5
6
B
7
8
C
910111213
Q
18
G
NC
17
Q
16
F
NC
15
14
Q
E
D
NC
Q
GND
CLK
CLR
over incoming data as a low at either input inhibits
entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables
the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed
while the clock is high or low, provided the minimum setup time requirements are met. Clocking occurs on the
low-to-high-level transition of the clock (CLK) input.
The SN54LV164A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LV164A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
OUTPUTS
A
QB...Q
B0QH0
AnQGn
AnQGn
AnQGn
H
Copyright 1998, Texas Instruments Incorporated
CLR CLK A B Q
L X X X L L L
H LXXQA0Q
H ↑ HHHQ
H ↑ LXLQ
H ↑ X L L Q
QA0, QB0, QH0 = the level of QA, QB, or QH, respectively,
before the indicated steady-state inputs conditions were
established
QAn, QGn = the level of QA or QG before the most recent
↑ transition of the clock: indicates a 1-bit shift
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
INPUTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54LV164A, SN74LV164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403B – APRIL 1998 – REVISED JUNE 1998
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
†
9
CLR
8
CLK C1/
1
A
2
B
SRG8
R
&
1D
logic diagram (positive logic)
8
CLK
10
11
12
13
3
Q
A
4
Q
B
5
Q
C
6
Q
D
Q
E
Q
F
Q
G
Q
H
1
A
2
B
9
CLR
Pin numbers shown are for the D, DB, DGV , J, NS, PW, and W packages.
C1
1D
R
345610111213
Q
A
1D
R
C1
C1
1D
R
Q
B
Q
C
1D
R
C1
C1
1D
R
Q
D
Q
E
1D
R
C1
C1
1D
R
Q
F
Q
G
1D
R
C1
Q
H
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical clear, shift, and clear sequences
CLR
A
B
Serial InputsOutputs
CLK
Q
A
Q
B
Q
C
Q
D
Q
E
SN54LV164A, SN74LV164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403B – APRIL 1998 – REVISED JUNE 1998
Q
F
Q
G
Q
H
Clear Clear
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
DB package 158°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 182°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 170°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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