Texas Instruments SN74LV164AD, SN74LV164ADBR, SN74LV164ADGVR, SN74LV164ADR, SN74LV164APWR Datasheet
SN54LV164A, SN74LV164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403B – APRIL 1998 – REVISED JUNE 1998
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Typical V
< 0.8 V at V
D
Typical V
(Output Ground Bounce)
OLP
, TA = 25°C
CC
(Output VOH Undershoot)
OHV
> 2 V at VCC, TA = 25°C
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
SN74LV164A. . . D, DB, DGV, NS, OR PW PACKAGE
SN54LV164A...J OR W PACKAGE
(TOP VIEW)
14
13
12
11
10
V
CC
Q
H
Q
G
Q
F
Q
E
CLR
9
CLK
8
Q
Q
Q
Q
GND
A
1
B
2
3
A
4
B
5
C
6
D
7
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
SN54LV164A. . . FK PACKAGE
(TOP VIEW)
BANC
V
CC
H
Q
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)
description
The ’LV164A devices are 8-bit parallel-out serial
shift registers designed for 2-V to 5.5-V V
operation.
These devices feature AND-gated serial (A and B)
inputs and an asynchronous clear (CLR) input.
The gated serial inputs permit complete control
CC
Q
NC
Q
NC
Q
NC – No internal connection
3212019
4
A
5
6
B
7
8
C
910111213
Q
18
G
NC
17
Q
16
F
NC
15
14
Q
E
D
NC
Q
GND
CLK
CLR
over incoming data as a low at either input inhibits
entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables
the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed
while the clock is high or low, provided the minimum setup time requirements are met. Clocking occurs on the
low-to-high-level transition of the clock (CLK) input.
The SN54LV164A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LV164A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
OUTPUTS
A
QB...Q
B0QH0
AnQGn
AnQGn
AnQGn
H
Copyright 1998, Texas Instruments Incorporated
CLR CLK A B Q
L X X X L L L
H LXXQA0Q
H ↑ HHHQ
H ↑ LXLQ
H ↑ X L L Q
QA0, QB0, QH0 = the level of QA, QB, or QH, respectively,
before the indicated steady-state inputs conditions were
established
QAn, QGn = the level of QA or QG before the most recent
↑ transition of the clock: indicates a 1-bit shift
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
INPUTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54LV164A, SN74LV164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403B – APRIL 1998 – REVISED JUNE 1998
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
†
9
CLR
8
CLK C1/
1
A
2
B
SRG8
R
&
1D
logic diagram (positive logic)
8
CLK
10
11
12
13
3
Q
A
4
Q
B
5
Q
C
6
Q
D
Q
E
Q
F
Q
G
Q
H
1
A
2
B
9
CLR
Pin numbers shown are for the D, DB, DGV , J, NS, PW, and W packages.
C1
1D
R
345610111213
Q
A
1D
R
C1
C1
1D
R
Q
B
Q
C
1D
R
C1
C1
1D
R
Q
D
Q
E
1D
R
C1
C1
1D
R
Q
F
Q
G
1D
R
C1
Q
H
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical clear, shift, and clear sequences
CLR
A
B
Serial InputsOutputs
CLK
Q
A
Q
B
Q
C
Q
D
Q
E
SN54LV164A, SN74LV164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403B – APRIL 1998 – REVISED JUNE 1998
Q
F
Q
G
Q
H
Clear Clear
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
DB package 158°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 182°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 170°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54LV164A, SN74LV164A
UNIT
VIHHigh-level input voltage
V
VILLow-level input voltage
V
IOHHigh-level output current
IOLLow-level output current
PARAMETER
TEST CONDITIONS
V
UNIT
V
V
V
V
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403B – APRIL 1998 – REVISED JUNE 1998
recommended operating conditions (see Note 4)
SN54LV164A SN74LV164A
MIN MAX MIN MAX
V
V
V
∆t/∆v Input transition rise or fall rate
T
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2 5.5 2 5.5 V
CC
VCC = 2 V 1.5 1.5
p
p
Input voltage 0 5.5 0 5.5 V
I
Output voltage 0 V
O
p
p
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
VCC = 2.3 V to 2.7 V VCC × 0.7 VCC × 0.7
VCC = 3 V to 3.6 V VCC × 0.7 VCC × 0.7
VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7
VCC = 2 V 0.5 0.5
VCC = 2.3 V to 2.7 V VCC × 0.3 VCC × 0.3
VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3
VCC = 4.5 V to 5.5 V VCC × 0.3 VCC × 0.3
CC
VCC = 2 V –50 –50 µA
VCC = 2.3 V to 2.7 V –2 –2
VCC = 3 V to 3.6 V –6 –6
VCC = 4.5 V to 5.5 V –12 –12
VCC = 2 V 50 50 µA
VCC = 2.3 V to 2.7 V 2 2
VCC = 3 V to 3.6 V 6 6
VCC = 4.5 V to 5.5 V 12 12
VCC = 2.3 V to 2.7 V 0 200 0 200
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V 0 20 0 20
, literature number SCBA004.
0 100 0 100
0 V
CC
V
mA
mA
ns/V
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV164A SN74LV164A
MIN TYP MAX MIN TYP MAX
IOH = –50 µA 2 V to 5.5 V VCC–0.1 VCC–0.1
OH
OL
I
I
I
CC
I
off
C
i
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
IOH = –2 mA 2.3 V 2 2
IOH = –6 mA 3 V 2.48 2.48
IOH = –12 mA 4.5 V 3.8 3.8
IOL = 50 µA 2 V to 5.5 V 0.1 0.1
IOL = 2 mA 2.3 V 0.4 0.4
IOL = 6 mA 3 V 0.44 0.44
IOL = 12 mA 4.5 V 0.55 0.55
VI = VCC or GND 5.5 V ±1 ±1 µA
VI = VCC or GND, IO = 0 5.5 V 20 20 µA
VI or VO = 0 to 5.5 V 0 V 5 5 µA
VI = VCC or GND 3.3 V 2.2 2.2 pF
CC
4
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UNIT
twPulse duration
ns
t
Set
ns
UNIT
twPulse duration
ns
t
Set
ns
UNIT
twPulse duration
ns
t
Set
ns
PARAMETER
UNIT
f
MH
C
15 pF
ns
C
pF
ns
SN54LV164A, SN74LV164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403B – APRIL 1998 – REVISED JUNE 1998
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54LV164A SN74LV164A
MIN MAX MIN MAX MIN MAX
CLR low 6 6.5 6.5
CLK high or low 6.5 7.5 7.5
su
t
h
up time
Hold time
Data before CLK↑ 6.5 8.5 8.5
inactive 3 3 3
CLR
Data after CLK↑ –0.5 0 0 ns
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54LV164A SN74LV164A
MIN MAX MIN MAX MIN MAX
CLR low 5 5 5
CLK high or low 5 5 5
su
t
h
up time
Hold time
Data before CLK↑ 5 6 6
inactive 2.5 2.5 2.5
CLR
Data after CLK↑ 0 0 0 ns
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54LV164A SN74LV164A
MIN MAX MIN MAX MIN MAX
CLR low 5 5 5
CLK high or low 5 5 5
su
t
h
up time
Hold time
Data before CLK↑ 4.5 4.5 4.5
CLR
inactive 2.5 2.5 2.5
Data after CLK↑ 1 1 1 ns
= 2.5 V± 0.2 V
CC
= 3.3 V ± 0.3 V
CC
= 5 V ± 0.5 V
CC
switching characteristics over recommended operating free-air temperature range,
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
V
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
max
tpd* CLK
t
* CLR
PHL
t
pd
t
PHL
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
CLK
CLR
Q
Q
Q
Q
CL = 15 pF* 55 105 50 50
CL = 50 pF 45 85 40 40
p
=
L
p
= 50
L
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TA = 25°C SN54LV164A SN74LV164A
MIN TYP MAX MIN MAX MIN MAX
9.2 17.6 1 20 1 20
8.6 16 1 18 1 18
11.5 21.1 1 24 1 24
10.8 19.5 1 22 1 22
z
5
SN54LV164A, SN74LV164A
PARAMETER
UNIT
f
MH
Q
C
F
ns
Q
C
50 pF
ns
PARAMETER
UNIT
f
MH
Q
C
15 pF
ns
Q
C
pF
ns
PARAMETER
UNIT
C
d
Power dissi ation ca acitance
C
L
MHz
F
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403B – APRIL 1998 – REVISED JUNE 1998
switching characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
max
tpd* CLK
t
* CLR
PHL
t
pd
t
PHL
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
CLK
CLR
CL = 15 pF* 80 155 65 65
CL = 50 pF 50 120 45 45
= 15 p
L
p
=
L
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
max
tpd* CLK
t
* CLR
PHL
t
pd
t
PHL
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
CLK
CLR
CL = 15 pF* 125 220 105 105
CL = 50 pF 85 165 75 75
=
L
p
= 50
L
TA = 25°C SN54LV164A SN74LV164A
MIN TYP MAX MIN MAX MIN MAX
6.4 12.8 1 15 1 15
6 12.8 1 15 1 15
8.3 16.3 1 18.5 1 18.5
7.9 16.3 1 18.5 1 18.5
TA = 25°C SN54LV164A SN74LV164A
MIN TYP MAX MIN MAX MIN MAX
4.5 9 1 10.5 1 10.5
4.2 8.6 1 10 1 10
6 11 1 12.5 1 12.5
5.8 10.6 1 12.5 1 12.5
z
z
noise characteristics, V
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
NOTE 5: Characteristics are for surface-mount packages only.
Quiet output, maximum dynamic V
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage 2.31 V
Low-level dynamic input voltage 0.99 V
= 3.3 V, CL = 50 pF, TA = 25°C (see Note 5)
CC
OL
OL
OH
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS V
p
p
p
p
= 50 F,f = 10
SN74LV164A
MIN TYP MAX
0.28 0.8 V
–0.22 –0.8 V
3.09 V
TYP UNIT
CC
3.3 V 48.1
5 V 47.5
p
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
(see Note A)
SN54LV164A, SN74LV164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403B – APRIL 1998 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
V
Test
Point
C
L
From Output
Under Test
(see Note A)
C
L
RL = 1 kΩ
S1
CC
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
Open
V
CC
GND
V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
t
w
Input
Input
In-Phase
Output
Out-of-Phase
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. t
F. t
G. t
50% V
CC
VOLTAGE WAVEFORMS
PULSE DURATION
50% V
CC
t
PLH
50% V
CC
t
PHL
50% V
CC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
PLZ
PZL
PHL
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PLH
3-STATE AND OPEN-DRAIN OUTPUTS
50% V
50% V
dis
CC
t
PHL
50% V
t
PLH
50% V
.
LOAD CIRCUIT FOR
V
CC
CC
0 V
V
CC
0 V
V
OH
CC
V
OL
V
OH
CC
V
OL
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at V
(see Note B)
Waveform 2
(see Note B)
CC
Output
S1 at GND
50% V
CC
t
CC
CC
h
50% V
50% V
CC
CC
VOL + 0.3 V
VOH – 0.3 V
t
su
50% V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
50% V
CC
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
t
PLZ
50% V
t
PHZ
50% V
V
CC
0 V
V
CC
0 V
V
CC
0 V
≈ V
V
OL
V
OH
≈ 0 V
CC
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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Copyright 1998, Texas Instruments Incorporated
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