Texas Instruments SN74LV161284DGGR, SN74LV161284DL, SN74LV161284DLR Datasheet

SN74LV161284

19-BIT BUS INTERFACE

SCLS426A – OCTOBER 1998 – REVISED FEBRUARY 1999

D

1.4-kΩ Pullup Resistors Integrated on All
Open-Drain Outputs Eliminate the Need for
Discrete Resistors

D

Designed for the IEEE Std 1284-I (Level-1
Type) and IEEE Std 1284-II (Level-2 Type)
Electrical Specifications

D

Flow-Through Architecture Optimizes PCB
Layout

D

Latch-Up Performance Exceeds 250 mA Per
JEDEC 17

D

Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin-Shrink
Small-Outline (DGG) Packages

description

The SN74LV161284 is designed for 4.5-V to

5.5-V V
asynchronous two-way communication between
data buses. The control-function implementation
minimizes external timing requirements.

This device has eight bidirectional bits; data can
flow in the A-to-B direction when DIR is high, and
in the B-to-A direction when DIR is low. This
device also has five drivers, which drive the cable
side, and four receivers. The SN74L V161284 has
one receiver dedicated to the HOST LOGIC line
and a driver to drive the PERI LOGIC line.

operation. This device provides

CC

DGG OR DL PACKAGE

HD

A9
A10
A1 1
A12
A13

V

CC

A1

A2

GND

A3

A4

A5

A6

GND

A7

A8

V

PERI LOGIC IN

HOST LOGIC OUT

CC

A14
A15
A16
A17

(TOP VIEW)

1

48

2

47

3

46

4

45

5

44

6

43

7

42

8

41

9

40

10

39

11

38

12

37

13

36

14

35

15

34

16

33

17

32

18

31

19

30

20

29

21

28

22

27

23

26

24

25

DIR
Y9
Y10
Y11
Y12
Y13

CABLE

V

CC

B1
B2
GND
B3
B4
B5
B6
GND
B7
B8

CABLE

V

CC

PERI LOGIC OUT
C14
C15
C16
C17
HOST LOGIC IN

The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the B, Y, and PERI
LOGIC OUT outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This
meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2
type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT, all
cable-side pins have a 1.4-kΩ integrated pullup resistor. The pullup resistor is switched off if the associated
output driver is in the low state or if the output voltage is above V

CABLE. If VCC CABLE is off, PERI LOGIC

CC

OUT is set to low.
The device has two supply voltages. V

is designed for 4.5-V to 5.5-V operation. VCC CABLE supplies the

CC

output buffers of the cable side only and is designed for 4.5-V to 5.5-V operation.
The SN74LV161284 is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1999, Texas Instruments Incorporated

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

SN74LV161284

OUTPUT

MODE

L

L

H

L

19-BIT BUS INTERFACE

SCLS426A – OCTOBER 1998 – REVISED FEBRUARY 1999

FUNCTION TABLE

INPUTS

DIR

logic diagram (positive logic)

HD

Open drain A9–A13 to Y9–Y13 and PERI LOGIC IN to PERI LOGIC OUT
Totem pole B1–B8 to A1–A8 and C14–C17 to A14–A17

L H Totem pole B1–B8 to A1–A8, A9–A13 to Y9–Y13, PERI LOGIC IN to PERI LOGIC OUT , and C14–C17 to A14–A17

Open drain A1–A8 to B1–B8, A9–A13 to Y9–Y13, and PERI LOGIC IN to PERI LOGIC OUT
Totem pole C14–C17 to A14–A17

H H Totem pole A1–A8 to B1–B8, A9–A13 to Y9–Y13, C14–C17 to A14–A17, and PERI LOGIC IN to PERI LOGIC OUT

VCC CABLE

DIR

HD

A1–A8

A9–A13

PERI LOGIC IN

42

48

1

19

See Note B

See Note B

See Note A

B1–B8

Y9–Y13

30

PERI LOGIC OUT

A14–A17

HOST LOGIC OUT

NOTES: A. The PMOS prevents backdriving current from the signal pins to VCC CABLE when VCC CABLE is open or at GND.

B. The PMOS prevents backdriving current from the signal pins to VCC CABLE when VCC CABLE is open or at GND. The PMOS

is turned off when the associated driver is in the low state.

2

24

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C14–C17

25

HOST LOGIC IN

VIHHigh-level input voltage

V

VILLow-level input voltage

V

VIInput voltage

V

SN74LV161284

19-BIT BUS INTERFACE

SCLS426A – OCTOBER 1998 – REVISED FEBRUARY 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range: V
Input and output voltage range, V
Input clamp current, I

Output clamp current, I
Continuous output current, I
Continuous current through each V
Output high sink current, I
Package thermal impedance, θ

CABLE –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

V

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

and VO: Cable side (see Notes 1 and 2) –2 V to 7 V. . . . . . . . . . . . . . . . . .

I

Peripheral side (see Note 1) –0.5 V to V

(VI < 0 or VI > VCC ) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

(VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(VO = 5.5 V and VCC CABLE = 5.5 V) 65 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . .

SK

JA

or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 3): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

†

+ 0.5 V. . . . . . . . . . .

DL package 94°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The ac input voltage pulse duration is limited to 40 ns if the amplitude is more negative than –0.5 V.

3. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 4)

MIN MAX UNIT

VCC CABLE Supply voltage for the cable side, VCC CABLE ≥ V
V

CC

V

O

I

OH

I

OL

T

A

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 4.5 5.5 V

p

p

p

Open-drain output voltage B, Y, and PERI LOGIC OUT (HD low) 0 5.5 V

High-level output current

Low-level output current

Operating free-air temperature –40 85 °C

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

CC

A, DIR, HD, and PERI LOGIC IN VCC × 0.7
B 2
C14–C17 2.3
HOST LOGIC IN 2.6
A, DIR, HD, and PERI LOGIC IN VCC × 0.3
B 0.8
C14–C17 0.8
HOST LOGIC IN 1.6
Peripheral side 0 V
Cable side 0 5.5

B and Y outputs (HD high) –14
A outputs and HOST LOGIC OUT
PERI LOGIC OUT –0.5
B and Y outputs 14
A outputs and HOST LOGIC OUT 8
PERI LOGIC OUT 84

4.5 5.5 V

CC

mA

–8

mA

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