Texas Instruments SN74LV139ADR, SN74LV139APWR, SN74LV139AD, SN74LV139ADBR, SN74LV139ADGVR Datasheet

SN54LV139A, SN74LV139A

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

SCLS396A – APRIL 1998 – REVISED OCTOBER 1998

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Process

D

Designed Specifically for High-Speed
Memory Decoders and Data-Transmission
Systems

D

Incorporate Two Enable Inputs to Simplify
Cascading and/or Data Reception

D

Latch-Up Performance Exceeds 250 mA Per
JESD 17

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V

SN74LV139A. . . D, DB, DGV, NS, OR PW PACKAGE

SN54LV139A...J OR W PACKAGE

(TOP VIEW)

1G

1A

1B
1Y0
1Y1
1Y2
1Y3

GND

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

V

CC

2G
2A
2B
2Y0
2Y1
2Y2

9

2Y3

Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)

description

The ’LV139A devices are dual 2-line to 4-line
decoders/demultiplexers designed for 2-V to

5.5-V V
These devices are designed for high-performance

memory-decoding or data-routing applications
requiring very short propagation delay times. In

operation.

CC

SN54LV139A. . . FK PACKAGE

1B

1Y0

NC
1Y1
1Y2

NC – No internal connection

(TOP VIEW)

1A1GNC

3212019

4
5
6
7
8

910111213

NC

1Y3

GND

CC

V

2Y3

2G

18
17
16
15
14

2Y2

2A
2B
NC
2Y0
2Y1

high-performance memory systems, these
decoders can minimize the effects of system decoding. When employed with high-speed memories utilizing a
fast enable circuit, the delay time of these decoders and the enable time of the memory are usually less than
the typical access time of the memory . This means that the effective system delay introduced by the decoders
is negligible.

The ’LV139A devices comprise two individual 2-line to 4-line decoders in a single package. The active-low
enable (G

) input can be used as a data line in demultiplexing applications. These decoders/demultiplexers

feature fully buffered inputs, each of which represents only one normalized load to its driving circuit.
The SN54LV139A is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74LV139A is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1998, Texas Instruments Incorporated

1

SN54LV139A, SN74LV139A

OUTPUTS

G

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

SCLS396A – APRIL 1998 – REVISED OCTOBER 1998

FUNCTION TABLE

INPUTS

SELECT

B A Y0 Y1 Y2 Y3

H X X H H H H

L L LLHHH
LLHHLHH
LHLHHLH

LHHHHHL

logic symbols (alternatives)

X/Y

2

1A

3

1B

1

1G

14

2A

13

2B

15

2G

†

These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.

1
2
EN

†

4

12
11

10

1Y0

5

1Y1

6

1Y2

7

1Y3

2Y0
2Y1

2Y2

9

2Y3

1A
1B

1G

2A
2B

2G

2
3
1

14
13
15

0
1

2

3

DMUX

0

G

1

0

0

1

3

2
3

12
11
10

4

1Y0

5

1Y1

6

1Y2

7

1Y3
2Y0

2Y1
2Y2

9

2Y3

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

SN54LV139A, SN74LV139A

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

SCLS396A – APRIL 1998 – REVISED OCTOBER 1998

4

1Y0

1

1G

2

1A

3

1B

15

2G

14

2A

13

2B

Pin numbers shown are for the D, DB, DGV , J, NS, PW, and W packages.

12

11

10

5

1Y1

6

1Y2

7

1Y3

2Y0

2Y1

2Y2

9

2Y3

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

(VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

(VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 3): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DB package 131°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 180°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 11 1° C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 149°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 7 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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