Texas Instruments SN74LV138AD, SN74LV138ADBR, SN74LV138ADGVR, SN74LV138ADR, SN74LV138APWR Datasheet
SN54LV138A, SN74LV138A
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS395B – APRIL 1998 – REVISED JUL Y 1998
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Typical V
< 0.8 V at V
D
Typical V
> 2 V at V
D
Latch-Up Performance Exceeds 250 mA Per
(Output Ground Bounce)
OLP
, TA = 25°C
CC
(Output VOH Undershoot)
OHV
, TA = 25°C
CC
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)
description
The ’LV138A devices are 3-line to 8-line
decoders/demultiplexers designed for 2-V to
5.5-V V
These devices are designed for high-
performance memory-decoding or data-routing
applications requiring very short propagation
delay times. In high-performance memory
operation.
CC
SN74LV138A. . . D, DB, DGV, NS, OR PW PACKAGE
SN54LV138A...J OR W PACKAGE
(TOP VIEW)
NC
16
15
14
13
12
11
10
9
CC
V
Y6
V
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y0
18
17
16
15
14
Y5
CC
Y1
Y2
NC
Y3
Y4
A
1
B
2
C
3
G2A
4
5
G2B
6
G1
7
Y7
GND
SN54LV138A. . . FK PACKAGE
C
G2A
NC
G2B
G1
NC – No internal connection
8
(TOP VIEW)
BANC
3212019
4
5
6
7
8
910111213
Y7
GND
systems, this decoder can be used to minimize the
effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay
times of this decoder and the enable time of the memory are usually less than the typical access time of the
memory. This means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select inputs (A, B, C) and the three enable inputs (G1, G2A
eight output lines. The two active-low (G2A
, G2B) and one active-high (G1) enable inputs reduce the need for
, G2B) select one of
external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters
and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing
applications.
The SN54L V138A is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LV138A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Copyright 1998, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54LV138A, SN74LV138A
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS395B – APRIL 1998 – REVISED JUL Y 1998
FUNCTION TABLE
ENABLE INPUTS
G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X H X X X X H H H H H H H H
X XHXXXHHHHHHHH
LXXXXXHHHHHHHH
HLLLLLLHHHHHHH
HLLLLHHLHHHHHH
HLLLHLHHLHHHHH
HLLLHHHHHLHHHH
HLLHLLHHHHLHHH
HLLHLHHHHHHLHH
HLLHHLHHHHHHLH
HL LHHHHHHHHHHL
SELECT INPUTS OUTPUTS
logic symbols (alternatives)
1
A
2
B
3
C
6
G1
4
G2A
5
G2B
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
BIN/OCT
1
2
4
&
EN
†
15
0
1
2
3
4
5
6
7
14
13
12
11
10
Y0
Y1
Y2
Y3
Y4
Y5
9
Y6
7
Y7
G1
G2A
G2B
1
A
2
B
3
C
6
4
5
DMUX
0
G
2
&
0
0
1
7
2
3
4
5
6
7
15
14
13
12
11
10
Y0
Y1
Y2
Y3
Y4
Y5
9
Y6
7
Y7
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1
A
SN54LV138A, SN74LV138A
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS395B – APRIL 1998 – REVISED JUL Y 1998
15
Y0
14
Y1
G1
G2A
G2B
2
B
3
C
6
4
5
13
12
11
10
Y2
Y3
Data
Outputs
Y4
Y5
9
Y6
7
Y7
Select
Inputs
Enable
Inputs
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
(VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 3): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DB package 131°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 180°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 11 1° C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 149°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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