Texas Instruments SN74LV126ANS Datasheet

SN54LV126A, SN74LV126A

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

SCES131C – MARCH 1998 – REVISED JUL Y 1998

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Process

D

Typical V
< 0.8 V at V

D

Typical V
> 2 V at V

D

Latch-Up Performance Exceeds 250 mA Per

(Output Ground Bounce)

OLP

, TA = 25°C

CC

(Output VOH Undershoot)

OHV

, TA = 25°C

CC

JESD 17

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)

description

These quadruple bus buffer gates are designed
for 2-V to 5.5-V V

The ’LV126A devices feature independent line
drivers with 3-state outputs. Each output is
disabled when the associated output-enable (OE)
input is low.

operation.

CC

SN74LV126A. . . D, DB, DGV, NS, OR PW PACKAGE

SN54LV126A...J OR W PACKAGE

(TOP VIEW)

1OE

1

1A

2

1Y

3

2OE

4

2A

5
6

2Y

7

GND

SN54LV126A. . . FK PACKAGE

1Y

NC

2OE

NC

2A

NC – No internal connection

(TOP VIEW)

1A

1OE

3212019

4
5
6
7
8

910111213

2Y

GND

NC

NC

14
13
12
11
10

9
8

CC

V

3Y

V

CC

4OE
4A
4Y
3OE
3A
3Y

4OE

18
17
16
15
14

3A

4A
NC
4Y
NC
3OE

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.

The SN54L V126A is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LV126A is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each buffer)

INPUTS

OE A

H H H
H LL

LXZ

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

OUTPUT

Y

EPIC is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1998, Texas Instruments Incorporated

1

SN54LV126A, SN74LV126A
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS

SCES131C – MARCH 1998 – REVISED JUL Y 1998

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.

†

1OE

1A

2OE

2A

3OE

3A

4OE

4A

1
2
4
5
10
9
13
12

EN

1

logic diagram (positive logic)

1

1OE

2

1A 1Y

4

2OE

3

3OE

3A 3Y

4OE

10

9

13

3

1Y

6

2Y

8

3Y

11

4Y

8

5

2A 2Y

Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.

6

12

4A 4Y

11

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ

Operating free-air temperature range, T
Storage temperature range, T

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 7 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

(VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

(VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 3): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DB package 158°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 182°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 170°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

A

‡

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

VIHHigh-level input voltage

V

VILLow-level input voltage

V

VOOutput voltage

V

IOHHigh-level output current

IOLLow-level output current

PARAMETER

TEST CONDITIONS

V

UNIT

V

V

V

V

SN54LV126A, SN74LV126A

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

SCES131C – MARCH 1998 – REVISED JUL Y 1998

recommended operating conditions (see Note 4)

SN54LV126A SN74LV126A

MIN MAX MIN MAX

V

V

∆t/∆v Input transition rise or fall rate

T

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 2 5.5 2 5.5 V

CC

VCC = 2 V 1.5 1.5

p

p

Input voltage 0 5.5 0 5.5 V

I

p

p

p

Operating free-air temperature –55 125 –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

VCC = 2.3 V to 2.7 V VCC × 0.7 VCC × 0.7
VCC = 3 V to 3.6 V VCC × 0.7 VCC × 0.7
VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7
VCC = 2 V 0.5 0.5
VCC = 2.3 V to 2.7 V VCC × 0.3 VCC × 0.3
VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3
VCC = 4.5 V to 5.5 V VCC × 0.3 VCC × 0.3

High or low state 0 V
3-state 0 5.5 0 5.5
VCC = 2 V –50 –50 µA
VCC = 2.3 V to 2.7 V –2 –2
VCC = 3 V to 3.6 V –8 –8
VCC = 4.5 V to 5.5 V –16 –16
VCC = 2 V 50 50 µA
VCC = 2.3 V to 2.7 V 2 2
VCC = 3 V to 3.6 V 8 8
VCC = 4.5 V to 5.5 V 16 16
VCC = 2.3 V to 2.7 V 0 200 0 200
VCC = 3 V to 3.6 V 0 100 0 100
VCC = 4.5 V to 5.5 V 0 20 0 20

, literature number SCBA004.

CC

0 V

CC

mA

mA

ns/V

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

I
I
I
I
C

OH

OL

I
OZ
CC
off

i

CC

IOH = –50 µA 2 V to 5.5 V VCC–0.1 VCC–0.1
IOH = –2 mA 2.3 V 2 2
IOH = –8 mA 3 V 2.48 2.48
IOH = –16 mA 4.5 V 3.8 3.8
IOL = 50 µA 2 V to 5.5 V 0.1 0.1
IOL = 2 mA 2.3 V 0.4 0.4
IOL = 8 mA 3 V 0.44 0.44
IOL = 16 mA 4.5 V 0.55 0.55
VI = VCC or GND 5.5 V ±1 ±1 µA
VO = VCC or GND 5.5 V ±5 ±5 µA
VI = VCC or GND, IO = 0 5.5 V 20 20 µA
VI or VO = 0 to 5.5 V 0 V 5 5 µA
VI = VCC or GND 3.3 V 1.6 1.6 pF

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LV126A SN74LV126A

MIN TYP MAX MIN TYP MAX

3