Datasheet SN54LS245FK, SN54LS245J, SN74LS245DBR, SN74LS245DW, SN74LS245DWR Datasheet (Texas Instruments)

SOIC

DW

LS245

CDIP

J

55°C to 125°C

SN54LS245, SN74LS245

OCTAL BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

SDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002

D

3-State Outputs Drive Bus Lines Directly

D

PNP Inputs Reduce dc Loading on Bus
Lines

D

Hysteresis at Bus Inputs Improves Noise
Margins

D

Typical Propagation Delay Times Port to
Port, 8 ns

I

OL

TYPE

SN54LS245 12 mA –12 mA
SN74LS245 24 mA –15 mA

(SINK

CURRENT)

I

OH

(SOURCE

CURRENT)

description

These octal bus transceivers are designed for
asynchronous two-way communication between
data buses. The control-function implementation
minimizes external timing requirements.

The devices allow data transmission from the
A bus to the B bus or from the B bus to the A bus,
depending on the logic level at the
direction-control (DIR) input. The output-enable
(OE

) input can disable the device so that the

buses are effectively isolated.

SN54LS245 ...J OR W PACKAGE

SN74LS245 ... DB, DW, N, OR NS PACKAGE

SN54LS245 . . . FK P ACKAGE

A3
A4
A5
A6
A7

(TOP VIEW)

1

DIR

2

A1

3

A2

4

A3

5

A4

6

A5

7

A6

8

A7

9

A8

GND

10

(TOP VIEW)

A2A1DIR

3 2 1 20 19

4
5
6
7
8

910111213

A8

B8

20
19
18
17
16
15
14
13
12
11

V

B7

CC

V
OE
B1
B2
B3
B4
B5
B6
B7
B8

OE

18
17
16
15
14

B6

CC

B1
B2
B3
B4
B5

GND

T

A

PDIP – N Tube SN74LS245N SN74LS245N

0°C to 70°C

SOP – NS Tape and reel SN74LS245NSR 74LS245
SSOP – DB T ape and reel SN74LS245DBR LS245

°

–

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

°

CFP – W Tube SNJ54LS245W SNJ54LS245W
LCCC – FK Tube SN54LS245FK SN54LS245FK

ORDERING INFORMA TION

PACKAGE

–

–

†

Tube SN74LS245DW
Tape and reel SN74LS245DWR

Tube SN54LS245J SN54LS245J
Tube SNJ54LS245J SNJ54LS245J

ORDERABLE

PART NUMBER

TOP-SIDE
MARKING

Copyright  2002, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

SN54LS245, SN74LS245

OPERATION

OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS

SDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002

schematics of inputs and outputs

FUNCTION TABLE

INPUTS

OE DIR

L L B data to A bus
L H A data to B bus

H X Isolation

EQUIVALENT OF EACH INPUT

V

CC

9 kΩ NOM

Input

logic diagram (positive logic)

DIR

TYPICAL OF ALL OUTPUTS

V

CC

50 Ω NOM

Output

1

19

OE

2

2

A1

To Seven Other Channels

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18

B1

UNIT

SN54LS245, SN74LS245

OCTAL BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

SDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V
Input voltage, V
Package thermal impedance,

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values are with respect to GND.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

q

(see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions

SN54LS245 SN74LS245

MIN NOM MAX MIN NOM MAX

V
I
I
T

OH
OL

Supply voltage 4.5 5 5.5 4.75 5 5.25 V

CC

High-level output current –12 –15 mA
Low-level output current 12 24 mA
Operating free-air temperature –55 125 0 70 °C

A

†

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3

SN54LS245, SN74LS245

PARAMETER

TEST CONDITIONS

†

UNIT

VOHHigh-level output voltage

V

2 V

V

VOLLow-level output voltage

V

2 V

V

I

t

V

MAX

mA

C

45 pF

R

667 W

t

Propagation delay time, high- to low-level output

8

12

C

45 pF

R

667 W

ns

C

5 pF

R

667 W

ns

OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS

SDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

SN54LS245 SN74LS245

MIN TYP‡MAX MIN TYP‡MAX

V

High-level input voltage 2 2 V

IH

V

Low-level input voltage 0.7 0.8 V

IL

V

Input clamp voltage VCC = MIN, II = –18 mA –1.5 –1.5 V

IK

Hysteresis (VT+ – VT–) A or B VCC = MIN 0.2 0.4 0.2 0.4 V

p

p

Off-state output current,

I

OZH

high-level voltage applied
Off-state output current,

I

OZL

low-level voltage applied
Input current at

maximum inpu

I

voltage

I

High-level input current VCC = MAX, VIH = 2.7 V 20 20 µA

IH

I

Low-level input current VCC = MAX, VIL = 0.4 V –0.2 –0.2 mA

IL

I

Short-circuit output current

OS

I

Supply current

CC

†

For conditions shown as MIN or MAX, use the appropriate values specified under recommended operating conditions.

‡

All typical values are at VCC = 5 V, TA = 25°C.

§

Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.

A or B

p

DIR or OE

§

Total, outputs high 48 70 48 70
Total, outputs low
Outputs at high Z 64 95 64 95

VCC = MIN,

VIL = V
VCC = MIN,

VIL = V
VCC = MAX,

OE
VCC = MAX,

OE

VCC = MAX –40 –225 40 –225 mA

VCC = MAX Outputs open

=

IH

=

IH

at 2 V

at 2 V

CC

,

IL(max)

,

IL(max)

=

IOH = –3 mA 2.4 3.4 2.4 3.4
IOH = MAX 2 2
IOL = 12 mA 0.4 0.4
IOL = 24 mA 0.5

VO = 2.7 V 20 20 µA

VO = 0.4 V –200 –200 µA

VI = 5.5 V 0.1 0.1
VI = 7 V 0.1 0.1

62 90 62 90

mA

switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)

PARAMETER TEST CONDITIONS MIN TYP MAX

t

PLH
PHL

t

PZL

t

PZH

t

PLZ

t

PHZ

Propagation delay time, low- to high-level output

p

Output enable time to low level
Output enable time to high level
Output disable time from low level
Output disable time from high level

p

,

=

L

p

,

=

L

p

,

=

L

UNIT

=

L

=

L

=

L

8 12

27 40
25 40
15 25
15 28

ns

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

From Output

Under Test

(see Note A)

Test

Point

C

L

SDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002

PARAMETER MEASUREMENT INFORMATION

SERIES 54LS/74LS DEVICES

V

CC

V

CC

R

L

R

(see Note B)

From Output

Under Test

(see Note A)

C

L

L

Test
Point

SN54LS245, SN74LS245

OCTAL BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

V

CC

From Output

Under Test

(see Note A)

Test

R

Point

C

L

L

S1

(see Note B)

5 kΩ

S2

FOR 2-STATE TOTEM-POLE OUTPUTS

High-Level

Low-Level

In-Phase

(see Note D)

Out-of-Phase

(see Note D)

NOTES: A. CL includes probe and jig capacitance.

LOAD CIRCUIT

Pulse

Pulse

Input

t

PLH

Output

t

PHL

Output

PROPAGATION DELAY TIMES

B. All diodes are 1N3064 or equivalent.

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

D. S1 and S2 are closed for t

E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns.

G. The outputs are measured one at a time with one input transition per measurement.

1.3 V 1.3 V

t

w

1.3 V 1.3 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

1.3 V 1.3 V

1.3 V 1.3 V

1.3 V 1.3 V

VOLTAGE WAVEFORMS

, t

PLH

PHL

t

PHL

t

PLH

, t

FOR OPEN-COLLECTOR OUTPUTS

PHZ

LOAD CIRCUIT

3 V

0 V

V

OH

V

OL

V

OH

V

OL

, and t

PLZ

Timing

Input

Data

Input

Output

Control

(low-level

enabling)

t

PZL

Waveform 1

(see Notes C

and D)

t

PZH

Waveform 2

(see Notes C

and D)

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

; S1 is open and S2 is closed for t

LOAD CIRCUIT

FOR 3-STATE OUTPUTS

1.3 V

t

su

1.3 V 1.3 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.3 V 1.3 V

1.3 V

1.3 V

VOLTAGE WAVEFORMS

; S1 is closed and S2 is open for t

PZH

3 V

0 V

t

h

3 V

0 V

3 V

0 V

t

PLZ

≈1.5 V
VOL + 0.5 V

V

OL

t

PHZ

V

OH

VOH – 0.5 V
≈1.5 V

.

PZL

Figure 1. Load Circuits and Voltage Waveforms

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5

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Copyright  2002, Texas Instruments Incorporated