Texas Instruments SN74LS224AN, SN74LS224AN3 Datasheet

SN74LS224A

16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY

WITH 3-STATE OUTPUTS

SDLS023C – JANUARY 1991 – REVISED DECEMBER 1999

OE

IR

LDCK

D0
D1
D2
D3

GND

N PACKAGE

(TOP VIEW)

1

16

2

15

3

14

4

13

5

12

6

11

7

10

8

9

V

CC

UNCK
OR
Q0
Q1
Q2
Q3
CLR

D

Independent Synchronous Inputs and
Outputs

D

16 Words by 4 Bits Each

D

3-State Outputs Drive Bus Lines Directly

D

Data Rates up to 10 MHz

D

Fall-Through Time 50 ns Typical

D

Data T erminals Arranged for Printed Circuit
Board Layout

D

Expandable Using External Gating

D

Packaged in Standard Plastic 300-mil DIPs

description

The SN74LS224A 64-bit, low-power Schottky memory is organized as 16 words by 4 bits each. It can be
expanded in multiples of 15m + 1 words or 4n bits, or both (where n is the number of packages in the vertical
array and m is the number of packages in the horizontal array); however, some external gating is required. For
longer words, the input ready (IR) signals of the first-rank packages and output ready (OR) signals of the
last-rank packages must be ANDed for proper synchronization.

A first-in, first-out (FIFO) memory is a storage device that allows data to be written to and read from its array
at independent data rates. These FIFOs are designed to process data at rates up to 10 MHz in a bit-parallel
format, word by word.

The load clock (LDCK) normally is held low, and data is written into memory on the high-to-low transition of
LDCK. The unload clock (UNCK) normally is held high, and data is read out on the low-to-high transition of
UNCK. The memory is full when the number of words clocked in exceeds by 16 the number of words clocked
out. When the memory is full, LDCK signals have no effect on the data residing in memory . When the memory
is empty, UNCK signals have no effect.

Status of the FIFO memory is monitored by the IR and OR flags that indicate not-full and not-empty conditions.
IR is high only when the memory is not full and LDCK is low. OR is high only when the memory is not empty
and UNCK is high.

A low level on the clear (CLR

) input resets the internal stack-control pointers and also sets IR high and OR low
to indicate that old data remaining at the data outputs is invalid. Data outputs are noninverting with respect to
the data inputs and are at high impedance when the output-enable (OE) input is low. OE does not af fect the IR
and OR outputs.

The SN74LS224A is characterized for operation from 0°C to 70°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1999, Texas Instruments Incorporated

1

SN74LS224A
16 × 4 SYNCHRONOUS FIRST -IN, FIRST-OUT MEMORY
WITH 3-STATE OUTPUTS

SDLS023C – JANUARY 1991 – REVISED DECEMBER 1999

logic symbol

†

This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. This symbol is functionally accurate but does
not show the details of implementation; for these, see the logic diagram. The symbol represents the memory as if it were controlled by a single
counter whose content is the number of words stored at the time. Output data is invalid when the counter content (CT) is 0.

†

FIFO 16 × 4

OE

CLR

LDCK

UNCK

D0
D1
D2
D3

1
9

3

15

4
5
6
7

EN5
CT = 0

CT < 16

CT > 0

1D

CTR

&

&

+ /C1

Z2

–

Z3

CT = 0

2

14

13
12
11
10

IR

OR

Q0
Q1
Q2
Q3

2

3

&

V4

2

4, 5

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

1

OE

9

CLR

3

LDCK

15

UNCK

4

D0

5

D1

6

D2

7

D3

S
1D

S
2D

R
3D

R
4D

C1

C2

C3

C4

SN74LS224A

16 × 4 SYNCHRONOUS FIRST -IN, FIRST-OUT MEMORY

WITH 3-STATE OUTPUTS

SDLS023C – JANUARY 1991 – REVISED DECEMBER 1999

Ring

Counter

CTR

DIV 16

+

Write

Address

CT = 1

Ring

Counter

CTR

DIV 16

+

Read

Address

CT = 1

1
2
3
4

5
6
7
8

9
10
11
12
13
14
15
16

16

1

2

3

4

5

6

7

8

9
10
11
12
13
14
15
16

16

16

16

COMP

Q=P+1

P

P=Q+1

Q

P=Q

EMPTY

RAM

16 × 4

1

1A

16

1

2A

16

C5

1A,5D 2A

EN

2

IR

14

OR

13

≥1

12
11
10

Q0
Q1

Q2
Q3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3