Texas Instruments SN74HSTL16918DGGR Datasheet

SN74HSTL16918

9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH

SCES096C – APRIL 1997 – REVISED JANUARY 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Member of the Texas Instruments
Widebus Family

D

Inputs Meet JEDEC HSTL Std JESD 8-6 and
Outputs Meet Level III Specifications

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 250 mA Per
JESD 17

D

Packaged in Plastic Thin Shrink
Small-Outline Package

description

This 9-bit to 18-bit D-type latch is designed for

3.15-V to 3.45-V V

CC

operation. The D inputs
accept HSTL levels and the Q outputs provide
L VTTL levels.

The SN74HSTL16918 is particularly suitable for
driving an address bus to two banks of memory.
Each bank of nine outputs is controlled with its
own latch-enable (LE

) input.

Each of the nine D inputs is tied to the inputs of two
D-type latches that provide true data (Q) at the
outputs. While LE

is low, the Q outputs of the
corresponding nine latches follow the D inputs.
When LE

is taken high, the Q outputs are latched

at the levels set up at the D inputs.
The SN74HSTL16918 is characterized for

operation from 0°C to 70°C.

FUNCTION TABLE

INPUTS

OUTPUT

LE D

Q

L H H
L LL
HXQ

0

†

†

Output level before the
indicated steady-state input
conditions were established

Copyright  1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments Incorporated.

DGG PACKAGE

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2Q1
1Q1

GND

D1
D2

V

CC

D3
D4

GND

1LE

GND

V

REF

GND

2LE

GND

D5
D6
D7

V

CC

D8
D9

GND

2Q9
1Q9

V

CC

V

CC

1Q2
2Q2
GND
1Q3
2Q3
V

CC

1Q4
2Q4
GND
1Q5
2Q5
GND
1Q6
2Q6
V

CC

1Q7
2Q7
GND
1Q8
2Q8
V

CC

V

CC

SN74HSTL16918
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH

SCES096C – APRIL 1997 – REVISED JANUARY 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

1Q1

2Q1

1LE

D1

2LE

To Eight Other Channels

2

1

10

4

14

1D

C1

1D

C1

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

CC

–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

O

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

IK

(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

OK

(VO < 0 or VO > VCC) (see Note 2) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I

O

(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through each V

CC

or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

JA

(see Note 3) 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This current flows only when the output is in the high state and VO > VCC.

3. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions (see Note 4)

MIN NOM MAX UNIT

V

CC

Supply voltage 3.15 3.45 V

V

REF

Reference voltage 0.68 0.75 0.9 V

V

I

Input voltage 0 1.5 V

V

IH

AC high-level input voltage All inputs V

REF

+200 mV V

V

IL

AC low-level input voltage All inputs V

REF

–200 mV V

V

IH

DC high-level input voltage All inputs V

REF

+100 mV V

V

IL

DC low-level input voltage All inputs V

REF

–100 mV V

I

OH

High-level output current –24 mA

I

OL

Low-level output current 24 mA

T

A

Operating free-air temperature 0 70 °C

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

SN74HSTL16918

9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH

SCES096C – APRIL 1997 – REVISED JANUARY 1999

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

IK

VCC = 3.15 V , II = –18 mA –1.2 V

V

OH

VCC = 3.15 V , IOH = –24 mA 2.4 V

V

OL

VCC = 3.15 V , IOL = 24 mA 0.5 V

Control inputs VI = 0 or 1.5 V ±5

I

I

Data inputs

VCC = 3.45 V

VI = 0 or 1.5 V ±5

µA

V

REF

V

REF

= 0.68 V or 0.9 V 90

I

CC

VCC = 3.45 V , VI = 0 or 1.5 V 50 100 mA

Control inputs VCC = 0 or 3.3 V, VI = 0 or 3.3 V 2

p

C

i

Data inputs VCC = 0 or 3.3 V, VI = 0 or 3.3 V 2.5

pF

C

o

Outputs VCC = 0, VO = 0 4 pF

†

All typical values are at VCC = 3.3 V, TA = 25°C.

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)

VCC = 3.3 V

± 0.15 V

UNIT

MIN MAX

t

w

Pulse duration, LE low 3 ns

t

su

Setup time, D before LE↑ 2 ns

t

h

Hold time D after LE↑ 1 ns

t

ldr

‡

Data race condition time D after LE↓ 0 ns

‡

This is the maximum time after LE switches low that the data input can return to the latched state from the opposite state without producing a
glitch on the output.

switching characteristics over recommended operating free-air temperature range, V

REF

= 0.75 V

PARAMETER

FROM

TO

VCC = 3.3 V

± 0.15 V

UNIT

(INPUT)

(OUTPUT)

MIN MAX

D

1.9 3.4

t

pd

LE

Q

1.9 4.2

ns

simultaneous switching characteristics over recommended operating free-air temperature range,
V

REF

= 0.75 V

§

PARAMETER

FROM

TO

VCC = 3.3 V

± 0.15 V

UNIT

(INPUT)

(OUTPUT)

MIN MAX

D

1.9 4.4

t

pd

LE

Q

1.9 5.2

ns

§

All outputs switching

SN74HSTL16918
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH

SCES096C – APRIL 1997 – REVISED JANUARY 1999

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

t

h

t

su

LOAD CIRCUIT

Data Input

V

REF

1.25 V

0.25 V

V

REF

V

REF

1.25 V

0.25 V

1.25 V

0.25 V

V

REF

t

w

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

t

PLH

t

PHL

V

REF

V

REF

1.25 V

0.25 V

V

OH

V

OL

Input

(see Note B)

Output

V

REF

From Output

Under Test

CL = 80 pF

(see Note A)

500 Ω

LE

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 1 ns, tf ≤ 1 ns.
C. The outputs are measured one at a time with one transition per measurement.
D. t

PHL

and t

PLH

are the same as tpd.

1.5 V 1.5 V

Figure 1. Load Circuit and Voltage Waveforms

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