SN74HSTL162822
14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
SCES091A – DECEMBER 1996 – REVISED APRIL 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus Family
D
Inputs Meet JEDEC HSTL Standard
JESD8-6
D
All Outputs Have Equivalent 25-Ω Series
Resistors
D
Packaged in Plastic Thin Shrink
Small-Outline Package
description
This 14-bit to 28-bit D-type latch is designed for
3.15-V to 3.45-V V
CC
operation. HSTL levels are
expected on the inputs. LVTTL levels are driven
on the Q outputs.
All outputs are designed to sink up to 12 mA and
include 25-Ω series resistors to reduce overshoot
and undershoot.
The SN74HSTL162822 is particularly suitable for
driving an address bus to two banks of memory.
Each bank of 14 outputs is controlled with its own
latch-enable (LE
) input.
Each of the 14 data (D) inputs is tied to the inputs
of two D-type latches, which provide true data at
the outputs. While LE is low, the outputs (Q) of the
corresponding 14 latches follow the D inputs.
When LE is taken high, the Q outputs are latched
at the levels set up at the D inputs.
The SN74HSTL162822 is characterized for
operation from –40°C to 90°C.
FUNCTION TABLE
INPUTS
OUTPUT
LE D
Q
L H H
L LL
H X Q
0
†
†
Output level before the
indicated steady-state input
conditions were established
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
DGG PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1Q2
2Q1
1Q1
GND
D1
D2
D3
V
CC
D4
D5
D6
GND
D7
1LE
V
CC
V
REF
GND
GND
2LE
D8
GND
D9
D10
D11
V
CC
D12
D13
D14
GND
1Q14
2Q14
1Q13
2Q2
1Q3
GND
2Q3
1Q4
V
CC
2Q4
1Q5
GND
2Q5
1Q6
V
CC
2Q6
1Q7
GND
2Q7
2Q8
GND
1Q8
2Q9
V
CC
1Q9
2Q10
GND
1Q10
2Q11
V
CC
1Q11
2Q12
GND
1Q12
2Q13
SN74HSTL162822
14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
SCES091A – DECEMBER 1996 – REVISED APRIL 1997
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1Q1
2Q1
1LE
D1
2LE
To 13 Other Channels
3
2
14
5
19
1D
C1
1D
C1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3) 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 4)
MIN NOM MAX UNIT
V
CC
Supply voltage 3.15 3.45 V
V
REF
Reference voltage 0.68 0.75 0.9 V
V
I
Input voltage 0 1.5 V
V
IH
High-level input voltage All pins V
REF
+100 mV V
V
IL
Low-level input voltage All pins V
REF
–100 mV V
I
OH
High-level output current –12
I
OL
Low-level output current 12
mA
T
A
Operating free-air temperature –40 90 °C
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
SN74HSTL162822
14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
SCES091A – DECEMBER 1996 – REVISED APRIL 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
VCC = 3.15 V , II = –18 mA –1.2 V
V
OH
VCC = 3.15 V , IOH = –12 mA 2.2 V
V
OL
VCC = 3.15 V , IOL = 12 mA 0.8 V
Control inputs VI = 0 or 1.5 V 5
I
I
Data inputs
VCC = 3.45 V
VI = 0 or 1.5 V 5
µA
V
REF
V
REF
= 0.68 V or 0.9 V 90
I
CC
VCC = 3.45 V , VI = 0 or 1.5 V 50 100 mA
Control inputs VCC = 0 or 3.3 V, VI = 0 or 3.3 V 2
p
C
i
Data inputs VCC = 0 or 3.3 V, VI = 0 or 3.3 V 2
pF
C
o
Outputs VCC = 0, VO = 0 4 pF
†
All typical values are at VCC = 3.3 V, TA = 25°C.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 3.3 V
± 0.15 V
UNIT
MIN MAX
t
w
Pulse duration, LE low 3 ns
t
su
Setup time, D before LE↑ 2 ns
t
h
Hold time, D after LE↑ 1 ns
switching characteristics over recommended operating free-air temperature range, V
REF
= 0.75 V
PARAMETER
FROM
TO
VCC = 3.3 V
± 0.15 V
UNIT
(INPUT)
(OUTPUT)
MIN MAX
D
1.6 5
t
pd
LE
Q
1.7 5.7
ns
SN74HSTL162822
14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
SCES091A – DECEMBER 1996 – REVISED APRIL 1997
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
t
h
t
su
LOAD CIRCUIT
Data Input
V
REF
1.25 V
0.25 V
V
REF
V
REF
1.25 V
0.25 V
1.25 V
0.25 V
V
REF
t
w
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLH
t
PHL
V
REF
V
REF
1.25 V
0.25 V
1.5 V 1.5 V
V
OH
V
OL
Input
(see Note B)
Output
V
REF
From Output
Under Test
CL = 80 pF
(see Note A)
500 Ω
LE
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 1 ns, tf≤ 1 ns.
C. The outputs are measured one at a time with one transition per measurement.
D. t
PHL
and t
PLH
are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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Copyright 1998, Texas Instruments Incorporated
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