Datasheet SN74HCT646NT3, SN74HCT646DW, SN74HCT646DWR, SN74HCT646NT Datasheet (Texas Instruments)
SN54HCT646, SN74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS178B – MARCH 1984 – REVISED MA Y 1997
D
Inputs Are TTL-Voltage Compatible
D
Independent Registers for A and B Buses
D
Multiplexed Real-Time and Stored Data
D
True Data Paths
D
High-Current 3-State Outputs Can Drive up
to 15 LSTTL Loads
D
Package Options Include Plastic
Small-Outline (DW) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (NT) and Ceramic (JT)
300-mil DIPs
description
The ’HCT646 consist of bus-transceiver circuits
with 3-state outputs, D-type flip-flops, and control
circuitry arranged for multiplexed transmission of
data directly from the input bus or from the internal
registers. Data on the A or B bus is clocked into the
registers on the low-to-high transition of the
appropriate clock (CLKAB or CLKBA) input.
Figure 1 illustrates the four fundamental busmanagement functions that can be performed
with the ’HCT646.
Output-enable (OE
inputs control the transceiver functions. In the
transceiver mode, data present at the
high-impedance port can be stored in either or
both registers.
The select-control (SAB and SBA) inputs can
multiplex stored and real-time (transparent mode)
data. DIR determines which bus receives data
when OE is active (low). In the isolation mode (OE
high), A data can be stored in one register and/or
B data can be stored in the other register.
) and direction-control (DIR)
SN54HCT646 . . . JT OR W PACKAGE
SN74HCT646 . . . DW OR NT PACKAGE
CLKAB
SN54HCT646 . . . FK PACKAGE
A1
A2
A3
NC
A4
A5
A6
NC – No internal connection
(TOP VIEW)
1
SAB
2
DIR
3
A1
4
A2
5
A3
6
A4
7
A5
8
A6
9
A7
10
A8
11
GND
5
6
7
8
9
10
11
12
(TOP VIEW)
DIR
SAB
4321 28
14 15 16 17
12 13
A8
A7
24
23
22
21
20
19
18
17
16
15
14
13
CLKAB
NC
NC
GND
CC
V
27 26
B8
CLKBA
V
CC
CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
B8
SBA
25
24
23
22
21
20
19
18
B7
B6
OE
B1
B2
NC
B3
B4
B5
When an output function is disabled, the input function is still enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
The SN54HCT646 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74HCT646 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54HCT646, SN74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS178B – MARCH 1984 – REVISED MA Y 1997
BUS A
21
OE OE
L
3
DIR
L
BUS A
1
23
CLKAB
REAL-TIME TRANSFER
BUS B TO BUS A
CLKBA
X
X
2
SAB
X
BUS B
22
SBA
L
BUS B
21
L
BUS A
3
DIR
H
BUS A
1
CLKAB
REAL-TIME TRANSFER
BUS A TO BUS B
CLKBA
X
23
BUS B
2
22
SAB
X
L
SBA
X
BUS B
21
X
X
H
Pin numbers shown are for the DW, JT, NT , and W packages.
3
DIR
X
X
X
1
CLKAB23CLKBA
↑
XX
STORAGE FROM
A, B, OR A AND B
2
22
SAB
X
↑
↑↑
SBA
X
X
X
X
X
Figure 1. Bus-Management Functions
2
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21
OEOE
L
L H H or L X H X
3
DIR
L
1
CLKAB
X
TRANSFER STORED DA TA
TO A AND/OR B
23
CLKBA
H or L
2
SAB
X
22
SBA
H
OPERATION OR FUNCTION
SN54HCT646, SN74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS178B – MARCH 1984 – REVISED MA Y 1997
FUNCTION TABLE
INPUTS
OE
X X ↑ X X X Input Unspecified
X XX ↑ X X Unspecified
H X ↑ ↑ X X Input Input Store A and B data
H X H or L H or L X X Input disabled Input disabled Isolation, hold storage
L L X X X L Output Input Real-time B data to A bus
L L X H or L X H Output Input Stored B data to A bus
L H X X L X Input Output Real-time A data to B bus
L H H or L X H X Input Output Stored A data to B bus
†
The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions are always enabled; i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.
DIR CLKAB CLKBA SAB SBA A1–A8 B1–B8
DATA I/O
†
†
Input Store B, A unspecified
Store A, B unspecified
†
†
logic symbol
‡
21
OE
DIR
CLKBA
SBA
CLKAB
SAB
A1
A2
A3
A4
A5
A6
A7
A8
3
23
22
1
2
4
5
6
7
8
9
10
11
G3
3 EN1 [BA]
3 EN2 [AB]
C4
G5
C6
G7
5
≥1
1
6D ≥1
5
7
7
1
20
19
18
17
16
15
14
13
B1
B2
B3
B4
B5
B6
B7
B8
4D
1
2
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, NT, and W packages.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54HCT646, SN74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS178B – MARCH 1984 – REVISED MA Y 1997
logic diagram (positive logic)
21
OE
3
DIR
SBA
SAB
23
22
1
2
CLKBA
CLKAB
One of Eight Channels
4
A1
1D
C1
To Seven Other Channels
Pin numbers shown are for the DW, JT, NT, and W packages.
absolute maximum ratings over operating free-air temperature range
C1
1D
20
B1
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
(VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
NT package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
PARAMETER
TEST CONDITIONS
V
UNIT
VOHV
V
or V
4.5 V
V
VOLV
V
V
4.5 V
V
V
UNIT
f
Clock frequenc
MH
twPulse duration, CLKBA or CLKAB high or lo
ns
t
S
CLKAB↑
CLKBA↑
ns
t
Hold ti
CLKAB↑
CLKBA↑
ns
SN54HCT646, SN74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS178B – MARCH 1984 – REVISED MA Y 1997
recommended operating conditions
SN54HCT646 SN74HCT646
MIN NOM MAX MIN NOM MAX
V
V
V
V
V
t
t
T
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
I
I
I
OZ
I
CC
∆I
C
†
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
CC
High-level input voltage VCC = 4.5 V to 5.5 V 2 2 V
IH
Low-level input voltage VCC = 4.5 V to 5.5 V 0 0.8 0 0.8 V
IL
Input voltage 0 V
I
Output voltage 0 V
O
Input transition (rise and fall) time 0 500 0 500 ns
Operating free-air temperature –55 125 –40 85 °C
A
CC
=
I
IH
=
or
I
IH
Control inputs VI = VCC or 0 5.5 V ±0.1 ±100 ±1000 ±1000 nA
A or B VO = VCC or 0 5.5 V ±0.01 ±0.5 ±10 ±5 µA
VI = VCC or 0, IO = 0 5.5 V 8 160 80 µA
CC
i
†
Control inputs
One input at 0.5 V or 2.4 V,
Other inputs at 0 or V
IOH = –20 µA
IL
IOH = –6 mA
IOL = 20 µA
IL
IOL = 6 mA
CC
5.5 V 1.4 2.4 3 2.9 mA
4.5 V
to 5.5 V
TA = 25°C SN54HCT646 SN74HCT646
MIN TYP MAX MIN MAX MIN MAX
4.4 4.499 4.4 4.4
3.98 4.3 3.7 3.84
0.001 0.1 0.1 0.1
0.17 0.26 0.4 0.33
3 10 10 10 pF
CC
CC
0 V
0 V
CC
CC
V
V
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C SN54HCT646 SN74HCT646
CC
MIN MAX MIN MAX MIN MAX
clock
su
h
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
etup time, A before
me, A after
y
or B before
or B after
w
4.5 V 0 31 0 22 0 27
5.5 V
4.5 V 16 23 19
5.5 V
4.5 V 20 30 25
5.5 V 18 27 23
4.5 V 5 5 5
5.5 V 5 5 5
0 36 0 24 0 29
14 21 17
z
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5
SN54HCT646, SN74HCT646
PARAMETER
V
UNIT
f
MH
CLKBA or CLKAB
A or B
tpdA or B
B or A
ns
SBA
SAB
†
A or B
t
OE
A or B
ns
t
OE
A or B
ns
tenDIR
A or B
ns
t
DIR
A or B
ns
ttAn
ns
PARAMETER
V
UNIT
CLKBA or CLKAB
A or B
tpdA or B
B or A
ns
SBA
SAB
†
A or B
OE
A or B
t
ns
DIR
A or B
ttAn
ns
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS178B – MARCH 1984 – REVISED MA Y 1997
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 2)
FROM TO
(INPUT) (OUTPUT)
max
or
en
dis
dis
y
†
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
CC
4.5 V 31 54 22 27
5.5 V 36 64 24 29
4.5 V 18 36 54 45
5.5 V 16 32 49 41
4.5 V 14 27 41 34
5.5 V 12 24 37 31
4.5 V 20 38 57 48
5.5 V 17 34 51 43
4.5 V 25 49 74 61
5.5 V 22 44 67 55
4.5 V 25 49 74 61
5.5 V 22 44 67 55
4.5 V 25 49 74 61
5.5 V 22 44 67 55
4.5 V 25 49 74 61
5.5 V 22 44 67 55
4.5 V 9 12 18 15
5.5 V 7 11 16 14
TA = 25°C SN54HCT646 SN74HCT646
MIN TYP MAX MIN MAX MIN MAX
z
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 2)
FROM TO
(INPUT) (OUTPUT)
or
en
y
†
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
CC
4.5 V 24 53 80 66
5.5 V 22 47 52 60
4.5 V 22 44 67 55
5.5 V 20 39 60 50
4.5 V 26 55 83 69
5.5 V 24 49 74 62
4.5 V 33 66 100 87
5.5 V 22 59 90 74
4.5 V 33 66 100 87
5.5 V 22 59 90 74
4.5 V 17 42 63 53
5.5 V 14 38 57 48
TA = 25°C SN54HCT646 SN74HCT646
MIN TYP MAX MIN MAX MIN MAX
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance No load 50 pF
pd
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT646, SN74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS178B – MARCH 1984 – REVISED MA Y 1997
PARAMETER MEASUREMENT INFORMATION
V
From Output
Under Test
(see Note A)
Test
Point
C
L
LOAD CIRCUIT
CC
S1
R
L
S2
PARAMETER C
t
t
PZH
t
PZL
t
PHZ
t
PLZ
t
en
t
dis
tpd or t
R
1 kΩ
1 kΩ
L
50 pF
150 pF
50 pF
50 pF
150 pF
L
or
Closed Open
Closed Open
or
S1
Open Closed
Open Closed
Open Open––
S2
High-Level
Pulse
Low-Level
Pulse
Input
In-Phase
Output
Out-of-
Phase
Output
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
1.3 V
t
t
1.3 V
t
w
1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V
PLH
90% 90%
t
r
PHL
1.3 V 1.3 V
10% 10%
t
f
VOLTAGE WAVEFORMS
1.3 V
1.3 V
t
PHL
t
PLH
3 V
0 V
3 V
0 V
1.3 V1.3 V
10%10%
90%90%
t
f
t
r
Reference
Input
t
su
Data
Input
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
3 V
0 V
V
V
V
V
OH
OL
OH
OL
Output
Control
(Low-Level
Enabling)
Output
Waveform 1
(See Note B)
Output
Waveform 2
(See Note B)
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
2.7 V 2.7 V
VOLTAGE WAVEFORMS
t
PZL
t
PZH
VOLTAGE WAVEFORMS
t
r
1.3 V
1.3 V
1.3 V
1.3 V
t
h
1.3 V
1.3 V1.3 V
0.3 V0.3 V
t
10%
90%
t
PLZ
PHZ
3 V
0 V
3 V
0 V
t
f
3 V
0 V
≈ V
CC
V
OL
V
OH
≈ 0 V
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. For clock inputs, f
E. The outputs are measured one at a time with one input transition per measurement.
F. t
G. t
H. t
PLZ
PZL
PLH
and t
and t
and t
PHZ
PZH
PHL
is measured when the input duty cycle is 50%.
max
are the same as t
are the same as ten.
are the same as tpd.
dis
.
Figure 2. Load Circuit and Voltage Waveforms
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7
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