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SN74HCT574PWLE

Datasheet SN74HCT574DW, SN74HCT574DWR, SN74HCT574N, SN74HCT574N3, SN74HCT574PWLE Datasheet (Texas Instruments)

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SN54HCT574, SN74HCT574
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS177C – MARCH 1984 – REVISED MA Y 1997
D
D
High-Current 3-State Noninverting Outputs Drive Bus Lines Directly or up to 15 LSTTL Loads
D
Bus-Structured Pinout
D
Package Options Include Plastic Small-Outline (DW), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
description
These octal edge-triggered D-type flip-flops feature 3-state outputs designed specifically for bus driving. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight flip-flops enter data on the low-to-high transition of the clock (CLK) input.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
SN54HCT574 ...J OR W PACKAGE
SN74HCT574 ...DW, N, OR PW PACKAGE
SN54HCT574 . . . FK PACKAGE
3D 4D 5D 6D 7D
(TOP VIEW)
OE
1
1D
2
2D
3
3D
4
4D
5
5D
6
6D
7
7D
8
8D
9
GND
10
(TOP VIEW)
2D1DOE
3212019
4 5 6 7 8
910111213
8D
GND
20 19 18 17 16 15 14 13 12 11
CLK
CC
V
8Q
V 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q CLK
1Q
18 17 16 15 14
7Q
CC
2Q 3Q 4Q 5Q 6Q
OE
does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state. The SN54HCT574 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HCT574 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
INPUTS
OE CLK D
L ↑ H H L ↑ LL L H or L X Q
H X X Z
OUTPUT
Q
0
Copyright 1997, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54HCT574, SN74HCT574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCLS177C – MARCH 1984 – REVISED MA Y 1997
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
OE
CLK
1D 2D 3D 4D 5D 6D 7D 8D
1 11
2 3 4 5 6 7 8 9
EN
C1
1D
logic diagram (positive logic)
1
OE
11
CLK
C1
1D
2
1D
19 18 17 16 15 14 13 12
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
19
1Q
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range
‡
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V Package thermal impedance, θ
or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 2): DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
PARAMETER
TEST CONDITIONS
V
UNIT
V
V
V
or V
4.5 V
V
V
V
V
V
4.5 V
V
V
UNIT
f
Clock frequenc
MH
twPulse duration, CLK high or lo
ns
t
Set
CLK↑
ns
t
Hold ti
CLK↑
ns
SN54HCT574, SN74HCT574
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS177C – MARCH 1984 – REVISED MA Y 1997
recommended operating conditions
SN54HCT574 SN74HCT574
MIN NOM MAX MIN NOM MAX
V V V V V t
t
T
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
†
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
CC
High-level input voltage VCC = 4.5 V to 5.5 V 2 2 V
IH
Low-level input voltage VCC = 4.5 V to 5.5 V 0 0.8 0 0.8 V
IL
Input voltage 0 V
I
Output voltage 0 V
O
Input transition (rise and fall) time 0 500 0 500 ns Operating free-air temperature –55 125 –40 85 °C
A
TA = 25°C SN54HCT574 SN74HCT574
MIN TYP MAX MIN MAX MIN MAX
4.4 4.499 4.4 4.4
3.98 4.3 3.7 3.84
0.001 0.1 0.1 0.1
0.17 0.26 0.4 0.33
3 10 10 10 pF
I I I
∆I
C
OH
OL
I OZ CC
i
CC
CC
=
I
IH
=
or
I
IH
VI = VCC or 0 5.5 V ±0.1 ±100 ±1000 ±1000 nA VO = VCC or 0 5.5 V ±0.01 ±0.5 ±10 ±5 µA VI = VCC or 0, IO = 0 5.5 V 8 160 80 µA One input at 0.5 V or 2.4 V,
†
Other inputs at 0 or V
IL
IL
IOH = –20 µA IOH = –6 mA IOL = 20 µA IOL = 6 mA
CC
5.5 V 1.4 2.4 3 2.9 mA
4.5 V
to 5.5 V
CC CC
0 V 0 V
CC CC
V V
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C SN54HCT574 SN74HCT574
CC
MIN MAX MIN MAX MIN MAX
clock
p
su
h
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
up time, data before
me, data after
y
w
4.5 V 0 30 0 20 0 24
5.5 V
4.5 V 16 24 20
5.5 V
4.5 V 20 30 25
5.5 V 17 27 23
4.5 V 5 5 5
5.5 V 5 5 5
0 33 0 22 0 27
14 22 18
z
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54HCT574, SN74HCT574
PARAMETER
V
UNIT
f
MH
tpdCLK
Any Q
ns
t
OE
Any Q
ns
t
OE
Any Q
ns
ttAny Q
ns
PARAMETER
V
UNIT
f
MH
tpdCLK
Any Q
ns
t
OE
Any Q
ns
ttAny Q
ns
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCLS177C – MARCH 1984 – REVISED MA Y 1997
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
FROM TO
(INPUT) (OUTPUT)
max
en
dis
CC
4.5 V 30 36 20 24
5.5 V 33 40 22 27
4.5 V 30 36 54 45
5.5 V 25 32 48 41
4.5 V 26 30 45 38
5.5 V 23 27 41 34
4.5 V 23 30 45 38
5.5 V 22 27 41 34
4.5 V 10 12 18 15
5.5 V 9 11 16 14
switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1)
FROM TO
(INPUT) (OUTPUT)
max
en
CC
4.5 V 30 36 20 24
5.5 V 33 40 22 27
4.5 V 40 53 80 66
5.5 V 35 47 71 60
4.5 V 34 47 71 59
5.5 V 29 39 94 78
4.5 V 18 42 63 53
5.5 V 16 38 57 48
TA = 25°C SN54HCT574 SN74HCT574
MIN TYP MAX MIN MAX MIN MAX
z
TA = 25°C SN54HCT574 SN74HCT574
MIN TYP MAX MIN MAX MIN MAX
z
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Power dissipation capacitance per flip-flop No load 93 pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT574, SN74HCT574
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS177C – MARCH 1984 – REVISED MA Y 1997
PARAMETER MEASUREMENT INFORMATION
V
From Output
Under Test
(see Note A)
Test
Point
C
L
LOAD CIRCUIT
CC
S1
R
L
S2
PARAMETER C
t
t
PZH
t
PZL
t
PHZ
t
PLZ
t
en
t
dis
tpd or t
R
1 kΩ
1 kΩ
L
50 pF
150 pF
50 pF
50 pF
150 pF
L
or
Closed Open
Closed Open
or
S1
Open Closed
Open Closed
Open Open––
S2
High-Level
Pulse
Low-Level
Pulse
Input
In-Phase
Output
Out-of-
Phase
Output
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
1.3 V
t
t
1.3 V
t
w
1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V
PLH
90% 90%
t
r
PHL
1.3 V 1.3 V 10% 10%
t
f
VOLTAGE WAVEFORMS
1.3 V
1.3 V
t
PHL
t
PLH
3 V
0 V
3 V
0 V
1.3 V1.3 V 10%10%
90%90%
t
f
t
r
Reference
Input
t
su
Data
Input
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
3 V
0 V
V
V
V
V
OH
OL
OH
OL
Output
Control
(Low-Level
Enabling)
Output
Waveform 1
(See Note B)
Output
Waveform 2
(See Note B)
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
2.7 V 2.7 V
VOLTAGE WAVEFORMS
t
PZL
t
PZH
VOLTAGE WAVEFORMS
t
r
1.3 V
1.3 V
1.3 V
1.3 V
t
h
1.3 V
1.3 V1.3 V
10%
90%
0.3 V0.3 V
t
PLZ
t
PHZ
3 V
0 V
3 V
0 V
t
f
3 V
0 V
≈ V
CC
V
OL
V
OH
≈ 0 V
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. For clock inputs, f
E. The outputs are measured one at a time with one input transition per measurement.
F. t G. t H. t
PLZ PZL PLH
and t and t
and t
PHZ PZH
PHL
is measured when the input duty cycle is 50%.
max
are the same as t are the same as ten.
are the same as tpd.
dis
.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
CERTAIN APPLICA TIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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