Datasheet JM38510-65761BRA, SN54HCT541J, SN74HCT541DBR, SN74HCT541DW, SN74HCT541DWR Datasheet (Texas Instruments)

SN54HCT541, SN74HCT541

OCTAL BUFFERS AND LINE DRIVERS

WITH 3-STATE OUTPUTS

SCLS306A – JANUARY 1996 – REVISED MA Y 1997

D

Inputs Are TTL-Voltage Compatible

D

High-Current 3-State Outputs Interface
Directly With System Bus or Can Drive up
to 15 LSTTL Loads

D

Data Flow-Through Pinout (All Inputs on
Opposite Side From Outputs)

D

Package Options Include Plastic
Small-Outline (DW) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs

description

These octal buffers and line drivers are designed
to have the performance of the popular ’HC240
series and to offer a pinout with inputs and outputs
on opposite sides of the package. This
arrangement greatly facilitates printed circuit
board layout.

The 3-state control gate is a 2-input NOR. If either
output-enable (OE1
outputs are in the high-impedance state. The
’HCT541 provide true data at the outputs.

The SN54HCT541 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HCT541 is characterized for
operation from –40°C to 85°C.

or OE2) input is high, all eight

SN54HCT541 ...J OR W PACKAGE

SN74HCT541 . . . DW OR N PACKAGE

SN54HCT541 . . . FK PACKAGE

A3
A4
A5
A6
A7

(TOP VIEW)

OE1

1

A1

2

A2

3

A3

4

A4

5

A5

6

A6

7

A7

8

A8

9

GND

10

(TOP VIEW)

A2A1OE1

3212019

4
5
6
7
8

910111213

A8

Y8

20
19
18
17
16
15
14
13
12
11

CC

V

Y7

V

CC

OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8

OE2

18
17
16
15
14

Y6

Y1
Y2
Y3
Y4
Y5

GND

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

FUNCTION TABLE

(each buffer/driver)

INPUTS

OE1 OE2 A

L L L L

L LH H
H XX Z
X H X Z

OUTPUT

Y

Copyright  1997, Texas Instruments Incorporated

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

SN54HCT541, SN74HCT541
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS

SCLS306A – JANUARY 1996 – REVISED MA Y 1997

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

†

OE1
OE2

A1
A2
A3

A4
A5
A6
A7
A8

1
19

2
3
4

5
6
7
8
9

&

EN

logic diagram (positive logic)

OE1
OE2

1
19

218

A1

Y1

18
17
16

15
14
13
12
11

Y1
Y2
Y3

Y4
Y5
Y6
Y7
Y8

To Seven Other Channels

absolute maximum ratings over operating free-air temperature range

‡

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through V
Package thermal impedance, θ

or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 2): DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

2

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UNIT

PARAMETER

TEST CONDITIONS

V

UNIT

V

V

V

or V

4.5 V

V

V

V

V

V

4.5 V

V

PARAMETER

V

UNIT

tpdA

Y

ns

t

OE

Y

ns

t

OE

Y

ns

ttY

ns

SN54HCT541, SN74HCT541

OCTAL BUFFERS AND LINE DRIVERS

WITH 3-STATE OUTPUTS

SCLS306A – JANUARY 1996 – REVISED MA Y 1997

recommended operating conditions

SN54HCT541 SN74HCT541

MIN NOM MAX MIN NOM MAX

V
V
V
V
V
t

t

T

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

†

This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.

Supply voltage 4.5 5 5.5 4.5 5 5.5 V

CC

High-level input voltage VCC = 4.5 V to 5.5 V 2 2 V

IH

Low-level input voltage VCC = 4.5 V to 5.5 V 0 0.8 0 0.8 V

IL

Input voltage 0 V

I

Output voltage 0 V

O

Input transition (rise and fall) time 0 500 0 500 ns
Operating free-air temperature –55 125 –40 85 °C

A

TA = 25°C SN54HCT541 SN74HCT541

MIN TYP MAX MIN MAX MIN MAX

4.4 4.499 4.4 4.4

3.98 4.3 3.7 3.84

0.001 0.1 0.1 0.1

0.17 0.26 0.4 0.33

3 10 10 10 pF

I
I
I

∆I

C

OH

OL

I
OZ
CC

i

CC

CC

=

I

IH

=

or

I

IH

VI = VCC or 0 5.5 V ±0.1 ±100 ±1000 ±1000 nA
VO = VCC or 0, VI = VIH or V
VI = VCC or 0, IO = 0 5.5 V 8 160 80 µA
One input at 0.5 V or 2.4 V,

†

Other inputs at 0 or V

IL

IL

IOH = –20 µA
IOH = –6 mA
IOL = 20 µA
IOL = 6 mA

CC

IL

5.5 V ±0.01 ±0.5 ±10 ±5 µA

5.5 V 1.4 2.4 3 2.9 mA

4.5 V

to 5.5 V

CC
CC

0 V
0 V

CC
CC

V
V

switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)

TA = 25°C SN54HCT541 SN74HCT541

MIN TYP MAX MIN MAX MIN MAX

en

dis

FROM TO

(INPUT) (OUTPUT)

CC

4.5 V 13 23 34 29

5.5 V 12 21 31 26

4.5 V 21 30 45 38

5.5 V 19 27 41 34

4.5 V 19 30 45 38

5.5 V 18 27 41 34

4.5 V 8 12 18 15

5.5 V 7 11 16 14

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3

SN54HCT541, SN74HCT541

PARAMETER

V

UNIT

tpdA

Y

ns

t

OE

Y

ns

ttY

ns

OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS

SCLS306A – JANUARY 1996 – REVISED MA Y 1997

switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)

FROM TO

(INPUT) (OUTPUT)

en

operating characteristics, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT

C

Power dissipation capacitance per buffer/driver No load 35 pF

pd

CC

4.5 V 20 33 49 42

5.5 V 19 30 45 38

4.5 V 26 40 60 50

5.5 V 25 36 54 45

4.5 V 17 42 63 53

5.5 V 14 38 57 48

TA = 25°C SN54HCT541 SN74HCT541

MIN TYP MAX MIN MAX MIN MAX

4

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SN54HCT541, SN74HCT541

OCTAL BUFFERS AND LINE DRIVERS

WITH 3-STATE OUTPUTS

SCLS306A – JANUARY 1996 – REVISED MA Y 1997

PARAMETER MEASUREMENT INFORMATION

V

From Output

Under Test

(see Note A)

Test

Point

C

L

LOAD CIRCUIT

CC

S1

R

L

S2

PARAMETER C

t

t

PZH

t

PZL

t

PHZ

t

PLZ

t

en

t

dis

tpd or t

R

1 kΩ

1 kΩ

L

50 pF

150 pF

50 pF

50 pF

150 pF

L

or

Closed Open

Closed Open

or

S1

Open Closed

Open Closed

Open Open––

S2

Input

Input

In-Phase

Output

Out-of-

Phase

Output

PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES

NOTES: A. CL includes probe and test-fixture capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following

D. The outputs are measured one at a time with one input transition per measurement.
E. t

F. t

G. t

1.3 V

t

PLH

90% 90%

t

PHL

1.3 V 1.3 V
10% 10%

VOLTAGE WAVEFORMS

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.

PLZ
PZL
PLH

and t
and t

and t

are the same as t

PHZ

are the same as ten.

PZH

are the same as tpd.

PHL

1.3 V

t

PHL

t

r

t

PLH

t

f

dis

2.7 V 2.7 V

VOLTAGE WAVEFORM

INPUT RISE AND FALL TIMES

1.3 V1.3 V

.

3 V

1.3 V1.3 V

0.3 V0.3 V

0 V

t

r

3 V

0 V

V

OH

10%10%

V

OL

t

f

V

OH

90%90%

V

OL

t

r

Output

Control

(Low-Level

Enabling)

Output

Waveform 1

(See Note B)

Output

Waveform 2

(See Note B)

ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS

t

f

1.3 V

t

PZL

t

PZH

VOLTAGE WAVEFORMS

1.3 V

1.3 V

1.3 V

t

PLZ

10%

90%

t

PHZ

3 V

0 V

≈ V

V

OL

V

OH

≈ 0 V

CC

Figure 1. Load Circuit and Voltage Waveforms

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Copyright  1998, Texas Instruments Incorporated