Texas Instruments SN74HCT257D, SN74HCT257DR, SN74HCT257N Datasheet
OE
Y
SN54HCT257, SN74HCT257
QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
WITH 3-STATE OUTPUTS
SCLS072B – NOVEMBER 1988 – REVISED MA Y 1997
D
Inputs Are TTL-Voltage Compatible
D
Provide Bus Interface From Multiple
Sources in High-Performance Systems
D
High-Current 3-State Outputs Interface
Directly With System Bus
D
Buffered Inputs and Outputs
D
Package Options Include Ceramic Chip
Carriers (FK) and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
The ’HCT257 are designed to multiplex signals
from 4-bit data sources to 4-output data lines in
bus-organized systems. The 3-state outputs do
not load the data lines when the output-enable
(OE) input is at the high logic level.
The SN54HCT257 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HCT257 is characterized for
operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
SELECT
A/B
H X X X Z
L L L XL
L L H XH
L H X LL
L H X H H
DATA
A B
OUTPUT
SN54HCT257 ...J PACKAGE
SN74HCT257 . . . N PACKAGE
SN54HCT257 . . . FK PACKAGE
1B
1Y
NC
2A
2B
NC – No internal connection
(TOP VIEW)
A/B
1
1A
2
1B
3
1Y
4
5
2A
6
2B
7
2Y
GND
8
(TOP VIEW)
1A
3212019
4
5
6
7
8
910111213
2Y
A/B
GND
NC
NC
16
15
14
13
12
11
10
9
V
3Y
CC
V
OE
4A
4B
4Y
3A
3B
3Y
OE
18
17
16
15
14
3B
CC
4A
4B
NC
4Y
3A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54HCT257, SN74HCT257
QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
WITH 3-STATE OUTPUTS
SCLS072B – NOVEMBER 1988 – REVISED MA Y 1997
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the J and N packages.
†
15
OE
A/B
1A
1B
2A
2B
3A
3B
4A
4B
1
2
3
5
6
11
10
14
13
EN
G1
1
1
MUX
logic diagram (positive logic)
15
OE
1
A
/B
12
4
1Y
7
2Y
9
3Y
4Y
2
1A
3
1B
5
2A
6
2B
11
3A
10
3B
14
4A
13
4B
Pin numbers shown are for the J and N packages.
12
4
1Y
7
2Y
9
3Y
4Y
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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