Texas Instruments SN74HCT00APWR, SN74HCT00D, SN74HCT00DR, SN74HCT00N, SN74HCT00PWLE Datasheet

SN54HCT00, SN74HCT00

QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SCLS062B – NOVEMBER 1988 – REVISED MA Y 1997

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Inputs Are TTL-Voltage Compatible

D

Package Options Include Plastic
Small-Outline (D), Thin Shrink
Small-Outline (PW), and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs

description

These devices contain four independent 2-input
NAND gates. They perform the Boolean function
Y = A

• B or Y = A + B in positive logic.

The SN54HCT00 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HCT00 is characterized for
operation from –40°C to 85°C.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A B

Y

H H L
L XH
X L H

logic symbol

†

1

1A

2

1B

1Y

3

4

2A

5

2B

2Y

6

9

3A

10

3B

3Y

8

12

4A

13

4B

4Y

11

&

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, J, N, PW, and W packages.

logic diagram (positive logic)

A
B

Y

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1
2
3
4
5
6
7

14
13
12
11
10

9
8

1A
1B
1Y
2A
2B
2Y

GND

V

CC

4B
4A
4Y
3B
3A
3Y

SN54HCT00 ...J OR W PACKAGE

SN74HCT00 . . . D, N, OR PW PACKAGE

(TOP VIEW)

3212019

910111213

4
5
6
7
8

18
17
16
15
14

4A
NC
4Y
NC
3B

1Y

NC

2A

NC

2B

1B1ANC

3Y

3A

V

4B

2Y

GND

NC

SN54HCT00 . . . FK PACKAGE

(TOP VIEW)

CC

NC – No internal connection

Copyright  1997, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

SN54HCT00, SN74HCT00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SCLS062B – NOVEMBER 1988 – REVISED MA Y 1997

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range

†

Supply voltage range, V

CC

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

JA

(see Note 2): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 170°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.

recommended operating conditions

SN54HCT00 SN74HCT00

MIN NOM MAX MIN NOM MAX

UNIT

V

CC

Supply voltage 4.5 5 5.5 4.5 5 5.5 V

V

IH

High-level input voltage VCC = 4.5 V to 5.5 V 2 2 V

V

IL

Low-level input voltage VCC = 4.5 V to 5.5 V 0 0.8 0 0.8 V

V

I

Input voltage 0 V

CC

0 V

CC

V

V

O

Output voltage 0 V

CC

0 V

CC

V

t

t

Input transition (rise and fall) time 0 500 0 500 ns

T

Az

Operating free-air temperature –55 125 –40 85 °C

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

TA = 25°C SN54HCT00 SN74HCT00

PARAMETER

TEST CONDITIONS

V

CC

MIN TYP MAX MIN MAX MIN MAX

UNIT

IOH = –20 µA

4.4 4.499 4.4 4.4

V

OH

V

I

=

V

IH

or

V

IL

IOH = –4 mA

4.5 V

3.98 4.3 3.7 3.84

V

IOL = 20 µA

0.001 0.1 0.1 0.1

V

OL

V

I

=

V

IH

or V

IL

IOL = 4 mA

4.5 V

0.17 0.26 0.4 0.33

V

I

I

VI = VCC or 0 5.5 V ±0.1 ±100 ±1000 ±1000 nA

I

CC

VI = VCC or 0, IO = 0 5.5 V 2 40 20 µA

∆I

CC

‡

One input at 0.5 V or 2.4 V ,
Other inputs at 0 or V

CC

5.5 V 1.4 2.4 3 2.9 mA

C

i

4.5 V

to 5.5 V

3 10 10 10 pF

‡

This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

SN54HCT00, SN74HCT00

QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SCLS062B – NOVEMBER 1988 – REVISED MA Y 1997

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)

FROM TO

TA = 25°C SN54HCT00 SN74HCT00

PARAMETER

(INPUT) (OUTPUT)

V

CC

MIN TYP MAX MIN MAX MIN MAX

UNIT

4.5 V 11 20 30 25

tpdA or B

Y

5.5 V 10 18 27 22

ns

4.5 V 9 15 22 19

ttY

5.5 V 8 14 20 17

ns

operating characteristics, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT

C

pd

Power dissipation capacitance per gate No load 20 pF

PARAMETER MEASUREMENT INFORMATION

VOLTAGE WAVEFORM

INPUT RISE AND FALL TIMES

1.3 V1.3 V

0.3 V0.3 V

2.7 V 2.7 V

3 V

0 V

t

r

t

f

Input

VOLTAGE WAVEFORMS

PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES

1.3 V

1.3 V1.3 V
10%10%

90% 90%

3 V

V

OH

V

OL

0 V

t

r

t

f

Input

In-Phase

Output

1.3 V

t

PLH

t

PHL

1.3 V 1.3 V
10% 10%

90%90%

V

OH

V

OL

t

r

t

f

t

PHL

t

PLH

Out-of-Phase

Output

Test
Point

From Output

Under Test

LOAD CIRCUIT

NOTES: A. CL includes probe and test-fixture capacitance.

B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following

characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. t

PLH

and t

PHL

are the same as tpd.

CL = 50 pF
(see Note A)

Figure 1. Load Circuit and Voltage Waveforms

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

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Copyright  1998, Texas Instruments Incorporated