Texas Instruments SN74HC682DW, SN74HC682DWR, SN74HC682N Datasheet

INPUTS

SN54HC682, SN74HC682

8-BIT MAGNITUDE COMPARATORS

SCLS018C – MARCH 1984 – REVISED MA Y 1997

D

Compare Two 8-Bit Words

D

100-kΩ Pullup Resistors Are on the
Q Inputs

D

Package Options Include Plastic
Small-Outline (DW) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs

description

These magnitude comparators perform
comparisons of two 8-bit binary or BCD words.
The ’HC682 feature 100-kΩ pullup termination
resistors on the Q inputs for analog or switch data.

The SN54HC682 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC682 is characterized for
operation from –40°C to 85°C.

FUNCTION TABLE

DATA

P, Q

P = Q L H
P > Q H L
P < Q H H

The P < Q function can be
generated by applying P = Q
and P > Q to a 2-input NAND
gate.

OUTPUTS

P = Q P > Q

SN54HC682 ...J OR W PACKAGE

SN74HC682 . . . DW OR N PACKAGE

P > Q

SN54HC682 . . . FK PACKAGE

P1

Q1

P2

Q2

P3

(TOP VIEW)

1

P0

2

Q0

3

P1

4

Q1

5

P2

6

Q2

7

P3

8

Q3

9

GND

10

(TOP VIEW)

Q0

3212019

4
5
6
7
8

910111213

Q3

P0

20
19
18
17
16
15
14
13
12
11

P > Q

VCCP = Q

P4

Q4

V

CC

P = Q
Q7
P7
Q6
P6
Q5
P5
Q4
P4

18
17
16
15
14

P5

Q7
P7
Q6
P6
Q5

GND

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1997, Texas Instruments Incorporated

1

SN54HC682, SN74HC682
8-BIT MAGNITUDE COMPARATORS

SCLS018C – MARCH 1984 – REVISED MA Y 1997

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

†

P0
P1
P2
P3

P4
P5
P6
P7

Q0
Q1
Q2
Q3

Q4
Q5
Q6
Q7

2
4
6
8

11
13
15
17

3
5
7
9

12
14
16
18

COMP

0

P = Q

P

7

0

P > Q

Q

7

19

P = Q

1

P > Q

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

2

P0

3

Q0

4

P1

5

Q1

6

P2

SN54HC682, SN74HC682

8-BIT MAGNITUDE COMPARATORS

SCLS018C – MARCH 1984 – REVISED MA Y 1997

19

P=Q

Q2

P3

Q3

P4

Q4

P5

Q5

P6

Q6

P7

7

8

9

11

12

13

14

15

16

17

1

P>Q

Q7

18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3