SN54HC652, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS151B – DECEMBER 1982 – REVISED MA Y 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Independent Registers and Enables for A
and B Buses
D
Multiplexed Real-Time and Stored Data
D
True Data Paths
D
High-Current 3-State Outputs Can Drive up
to 15 LSTTL Loads
D
Package Options Include Plastic
Small-Outline (DW) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (NT) and Ceramic (JT)
300-mil DIPs
description
These devices consist of bus-transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.
Output-enable (OEAB and OEBA
) inputs are
provided to control the transceiver functions.
Select-control (SAB and SBA) inputs are provided
to select real-time or stored data transfer. A low
input level selects real-time data, and a high input
level selects stored data. Figure 1 illustrates the
four fundamental bus-management functions that
can be performed with the ’HC652.
Data on the A or B data bus, or both, can be stored
in the internal D-type flip-flops by low-to-high
transitions at the appropriate clock (CLKAB or
CLKBA) terminals regardless of the select- or
output-control terminals. When SAB and SBA are
in the real-time transfer mode, it is possible to
store data without using the internal D-type
flip-flops by simultaneously enabling OEAB and
OEBA
. In this configuration, each output
reinforces its input. When all other data sources to
the two sets of bus lines are at high impedance,
each set of bus lines remains at its last state.
The SN54HC652 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HC652 is characterized for operation from –40°C to 85°C.
Copyright 1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54HC652 . . . JT OR W PACKAGE
SN74HC652 . . . DW OR NT PACKAGE
(TOP VIEW)
SN54HC652 . . . FK PACKAGE
(TOP VIEW)
NC – No internal connection
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLKAB
SAB
OEAB
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
CLKBA
SBA
OEBA
B1
B2
B3
B4
B5
B6
B7
B8
321
13 14
5
6
7
8
9
10
11
OEBA
B1
B2
NC
B3
B4
B5
A1
A2
A3
NC
A4
A5
A6
4
15 16 17 18
A8
GND
NC
B8B7B6
OEAB
SAB
CLKAB
NC
28 27 26
12
A7
CLKBA
SAB
CC
V
25
24
23
22
21
20
19
SN54HC652, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS151B – DECEMBER 1982 – REVISED MA Y 1997
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
OEAB
X
L
L
OEAB
LL
CLKABXCLKBAXSABXSBA
L
CLKABXCLKBAXSABLSBA
X
H
CLKAB CLKBAXSABXSBA
X
CLKAB CLKBA SAB SBA
X
H
XX
X
X
X
H L H or L H H
↑
↑
↑↑
OEBA
OEBA
HH
OEAB OEBA
OEAB OEBA
H or L
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
3 21 1 23 2 22 1 23 2 22321
3 21 23 2 22 3 21 1 2 22
1
23
Pin numbers shown are for the DW, JT, NT, and W packages.
Figure 1. Bus-Management Functions
SN54HC652, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS151B – DECEMBER 1982 – REVISED MA Y 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
DATA I/O
†
OEAB OEBA CLKAB CLKBA SAB SBA A1–A8 B1–B8
OPERATION OR FUNCTION
L H H or L H or L X X Input Input Isolation
L H ↑↑X X Input Input Store A and B data
X H ↑ H or L X X Input Unspecified
‡
Store A, hold B
H H ↑↑X
‡
X Input Output Store A in both registers
L X H or L ↑ X X Unspecified
‡
Input Hold A, store B
L L ↑↑XX‡Output Input Store B in both registers
L L X X X L Output Input Real-time B data to A bus
L L X H or L X H Output Input Stored B data to A bus
H H X X L X Input Output Real-time A data to B bus
H H H or L X H X Input Output Stored A data to B bus
H L H or L H or L H H Output Output
Stored A data to B bus and
stored B data to A bus
†
The data-output functions are enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions are always enabled;
i.e., data at the bus terminals is stored on every low-to-high transition on the clock inputs.
‡
Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.
logic symbol
§
§
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, NT, and W packages.
OEBA
EN1 [BA]
21
G5
22
SBA
A1
4
B1
20
4D
EN2 [AB]
3
OEAB
23
CLKBA
1
CLKAB
G7
2
SAB
5
7
7
5
1
1
6D ≥1
≥1
1
2
C6
C4
A2
5
B2
19
A3
6
B3
18
A4
7
B4
17
A5
8
B5
16
A6
9
B6
15
A7
10
B7
14
A8
11
B8
13
SN54HC652, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS151B – DECEMBER 1982 – REVISED MA Y 1997
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
Pin numbers shown are for the DW, JT, NT, and W packages.
OEBA
A1
B1
1D
C1
1D
C1
One of Eight Channels
SAB
CLKAB
SBA
CLKBA
OEAB
To Seven Other Channels
21
3
23
22
1
2
4
20
absolute maximum ratings over operating free-air temperature range
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NT package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
SN54HC652, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS151B – DECEMBER 1982 – REVISED MA Y 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
SN54HC652 SN74HC652
MIN NOM MAX MIN NOM MAX
UNIT
V
CC
Supply voltage 2 5 6 2 5 6 V
VCC = 2 V 1.5 1.5
V
IH
High-level input voltage
VCC = 4.5 V
3.15 3.15
V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
V
IL
Low-level input voltage
VCC = 4.5 V
0 1.35 0 1.35
V
VCC = 6 V 0 1.8 0 1.8
V
I
Input voltage 0 V
CC
0 V
CC
V
V
O
Output voltage 0 V
CC
0 V
CC
V
VCC = 2 V 0 1000 0 1000
t
t
Input transition (rise and fall) time
VCC = 4.5 V
0 500 0 500
ns
VCC = 6 V 0 400 0 400
T
A
Operating free-air temperature –55 125 –40 85 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54HC652 SN74HC652
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA
4.5 V 4.4 4.499 4.4 4.4
V
OH
VI = VIH or V
IL
6 V 5.9 5.999 5.9 5.9
V
IOH = –6 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –7.8 mA 6 V 5.48 5.8 5.2 5.34
2 V 0.002 0.1 0.1 0.1
IOL = 20 µA
4.5 V 0.001 0.1 0.1 0.1
V
OL
VI = VIH or V
IL
6 V 0.001 0.1 0.1 0.1
V
IOL = 6 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 7.8 mA 6 V 0.15 0.26 0.4 0.33
I
I
Control
inputs
VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
I
OZ
A or B VO = VCC or GND 6 V ±0.01 ±0.5 ±10 ±5 µA
I
CC
VI = VCC or 0, IO = 0 6 V 8 160 80 µA
C
i
Control
inputs
2 V to 6 V 3 10 10 10 pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54HC652, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS151B – DECEMBER 1982 – REVISED MA Y 1997
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C SN54HC652 SN74HC652
V
CC
MIN MAX MIN MAX MIN MAX
UNIT
2 V 0 6 0 4.3 0 5.5
f
clock
Clock frequency
4.5 V
0 31 0 22 0 27
MHz
6 V 0 36 0 25 0 31
2 V 80 115 95
t
w
Pulse duration, CLKBA or CLKAB high or low
4.5 V
16 23 19
ns
6 V 14 20 16
2 V 100 150 125
t
su
Setup time, A before CLKAB↑or B before CLKBA
↑
4.5 V 20 30 25
ns
6 V 17 26 21
2 V 5 5 5
t
h
Hold time, A after CLKAB↑or B after CLKBA
↑
4.5 V 5 5 5
ns
6 V 5 5 5
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 2)
FROM TO
TA = 25°C SN54HC652 SN74HC652
PARAMETER
(INPUT) (OUTPUT)
V
CC
MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 6 10 4.3 5.5
f
max
4.5 V 31 40 22 27
MHz
6 V 36 45 25 31
2 V 65 180 270 225
CLKBA or CLKAB A or B
4.5 V 18 36 54 45
6 V 14 31 46 38
2 V 50 135 205 170
t
pd
A or B B or A
4.5 V 14 27 41 34
ns
6 V 11 23 35 29
2 V 70 190 285 240
SBA or SAB
†
A or B
4.5 V 20 38 57 48
6 V 16 32 48 41
2 V 85 245 370 305
t
en
OEBA or OEAB A or B
4.5 V 25 49 74 61
ns
6 V 20 42 63 52
2 V 50 245 370 305
t
dis
OEBA or OEAB A or B
4.5 V 23 49 74 61
ns
6 V 20 42 63 52
2 V 28 60 90 75
t
t
Any
4.5 V 8 12 18 15
ns
6 V 6 10 15 13
†
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54HC652, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS151B – DECEMBER 1982 – REVISED MA Y 1997
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 2)
FROM TO
TA = 25°C SN54HC652 SN74HC652
PARAMETER
(INPUT) (OUTPUT)
V
CC
MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 90 265 400 330
CLKBA or CLKAB A or B
4.5 V 24 53 80 66
6 V 18 46 68 57
2 V 70 220 335 275
t
pd
A or B B or A
4.5 V 20 44 70 55
ns
6 V 15 38 57 48
2 V 80 275 415 345
SBA or SAB
†
A or B
4.5 V 24 55 83 69
6 V 20 47 70 60
2 V 100 330 500 410
t
en
OEBA or OEAB A or B
4.5 V 33 66 100 82
ns
6 V 27 57 85 71
2 V 45 210 315 265
t
t
Any
4.5 V 17 42 63 53
ns
6 V 13 36 53 43
†
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
pd
Power dissipation capacitance No load 50 pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54HC652, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS151B – DECEMBER 1982 – REVISED MA Y 1997
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
t
h
t
su
50%
50%50%
10%10%
90% 90%
V
CC
V
CC
0 V
0 V
t
r
t
f
Reference
Input
Data
Input
50%
High-Level
Pulse
50%
V
CC
0 V
50%
50%
V
CC
0 V
t
w
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%50%
10%10%
90% 90%
V
CC
V
OH
V
OL
0 V
t
r
t
f
Input
In-Phase
Output
50%
t
PLH
t
PHL
50% 50%
10% 10%
90%90%
V
OH
V
OL
t
r
t
f
t
PHL
t
PLH
Out-of-
Phase
Output
50%
10%
90%
V
CC
≈ V
CC
V
OL
0 V
Output
Control
(Low-Level
Enabling)
Output
Waveform 1
(See Note B)
50%
t
PZL
t
PLZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
V
OH
≈ 0 V
50%
50%
t
PZH
t
PHZ
Output
Waveform 2
(See Note B)
≈ V
CC
Test
Point
From Output
Under Test
R
L
V
CC
S1
S2
LOAD CIRCUIT
PARAMETER C
L
t
PZH
tpd or t
t
t
dis
t
en
t
PZL
t
PHZ
t
PLZ
1 kΩ
1 kΩ
50 pF
or
150 pF
50 pF
Open Closed
R
L
S1
Closed Open
S2
Open Closed
Closed Open
50 pF
or
150 pF
Open Open––
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily . All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. For clock inputs, f
max
is measured when the input duty cycle is 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. t
PLZ
and t
PHZ
are the same as t
dis
.
G. t
PZL
and t
PZH
are the same as ten.
H. t
PLH
and t
PHL
are the same as tpd.
C
L
(see Note A)
Figure 2. Load Circuit and Voltage Waveforms
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERSTOOD T O
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
Loading...