Texas Instruments SN74HC646DW, SN74HC646DWR, SN74HC646NT, SN74HC646NT3 Datasheet

SN54HC646, SN74HC646

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCLS150B – DECEMBER 1982 – REVISED MA Y 1997

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Independent Registers for A and B Buses

D

Multiplexed Real-Time and Stored Data

D

True Data Paths

D

High-Current 3-State Outputs Can Drive up
to 15 LSTTL Loads

D

Package Options Include Plastic
Small-Outline (DW) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (NT) and Ceramic (JT)
300-mil DIPs

description

The ’HC646 consist of bus-transceiver circuits
with 3-state outputs, D-type flip-flops, and control
circuitry arranged for multiplexed transmission of
data directly from the input bus or from the internal
registers. Data on the A or B bus is clocked into the
registers on the low-to-high transition of the
appropriate clock (CLKAB or CLKBA) input.
Figure 1 illustrates the four fundamental bus­management functions that can be performed
with the ’HC646.

Output-enable (OE) and direction-control (DIR)
inputs control the transceiver functions. In the
transceiver mode, data present at the
high-impedance port may be stored in either or
both registers.

The select-control (SAB and SBA) inputs can
multiplex stored and real-time (transparent mode)
data. DIR determines which bus receives data
when OE

is active (low). In the isolation mode (OE
high), A data may be stored in one register and/or
B data may be stored in the other register.

When an output function is disabled, the input function is still enabled and can be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.

The SN54HC646 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HC646 is characterized for operation from –40°C to 85°C.

Copyright  1997, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

14 15 16 17

SN54HC646 . . . JT OR W PACKAGE

SN74HC646 . . . DW OR NT PACKAGE

(TOP VIEW)

SN54HC646 . . . FK PACKAGE

(TOP VIEW)

CLKAB

SAB

DIR

A1
A2
A3
A4
A5
A6
A7
A8

GND

V

CC

CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
B8

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

5
6
7
8
9
10
11

25
24
23
22
21
20
19

4321 28

12 13

OE
B1
B2
NC
B3
B4
B5

A1
A2
A3

NC

A4
A5
A6

DIR

SAB

CLKAB

B8

B7

A8

GND

NC

NC

CLKBA

SBA

V

A7

B6

18

27 26

CC

NC – No internal connection

SN54HC646, SN74HC646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCLS150B – DECEMBER 1982 – REVISED MA Y 1997

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

21

L

3

DIR

L

1

CLKAB

X

23

CLKBA

X

2

SAB

X

22

SBA

L

REAL-TIME TRANSFER

BUS B TO BUS A

21

L

3

DIR

H

1

CLKAB

X

23

CLKBA

X

2

SAB

L

22

SBA

X

REAL-TIME TRANSFER

BUS A TO BUS B

21

X

3

DIR

X

1

CLKAB23CLKBA

X

2

SAB

X

22

SBA

X

STORAGE FROM
A, B, OR A AND B

21

L

3

DIR

L

1

CLKAB

X

23

CLKBA

H or L

2

SAB

X

22

SBA

H

TRANSFER STORED DATA

TO A AND/OR B

X
H

X
X

XX

X

X
X

L H H or L X H X

↑

↑
↑↑

BUS B

BUS A

BUS B

BUS A

BUS B

BUS A

BUS B

BUS A

OE OE

OEOE

Pin numbers shown are for the DW, JT, NT, and W packages.

Figure 1. Bus-Management Functions

SN54HC646, SN74HC646

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCLS150B – DECEMBER 1982 – REVISED MA Y 1997

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLE

INPUTS

DATA I/O

OE DIR CLKAB CLKBA SAB SBA A1–A8 B1–B8

OPERATION OR FUNCTION

X X ↑ X X X Input Unspecified

†

Store A, B unspecified

†

X XX ↑ X X Unspecified

†

Input Store B, A unspecified

†

H X ↑ ↑ X X Input Input Store A and B data
H X H or L H or L X X Input disabled Input disabled Isolation, hold storage
L L X X X L Output Input Real-time B data to A bus
L L X H or L X H Output Input Stored B data to A bus
L H X X L X Input Output Real-time A data to B bus
L H H or L X H X Input Output Stored A data to B bus

†

The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions are always enabled; i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.

logic symbol

‡

‡

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DW, JT, NT, and W packages.

A1

4

B1

20

4D

5

7

7

5

1

1

6D ≥1

≥1

1

2

A2

5

B2

19

A3

6

B3

18

A4

7

B4

17

A5

8

B5

16

A6

9

B6

15

A7

10

B7

14

A8

11

B8

13

OE

G3

21

3 EN2 [AB]

G5

22

SBA

3 EN1 [BA]

3

DIR

23

CLKBA

1

CLKAB

G7

2

SAB

C6

C4