Texas Instruments SN54HC595J, SN74HC595D, SN74HC595DR, SN74HC595DW, SN74HC595DWR Datasheet
...
SN54HC595, SN74HC595
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS041B – DECEMBER 1982 – REVISED MA Y 1997
D
8-Bit Serial-In, Parallel-Out Shift
D
High-Current 3-State Outputs Can Drive up
to 15 LSTTL Loads
D
Shift Register Has Direct Clear
D
Package Options Include Plastic
Small-Outline (D) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
description
The ’HC595 contain an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. The storage register has parallel 3-state
outputs. Separate clocks are provided for both the
shift and storage register. The shift register has a
direct overriding clear (SRCLR
(SER) input, and serial outputs for cascading.
Both the shift register clock (RCLK) and storage
register clock (SRCLK) are positive-edge triggered. If both clocks are connected together, the
shift register is always one clock pulse ahead of
the storage register.
The SN54HC595 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC595 is characterized for
operation from –40°C to 85°C.
) input, serial
SN54HC595 ...J OR W PACKAGE
SN74HC595 ...D OR N PACKAGE
SN54HC595 . . . FK PACKAGE
Q
D
Q
E
NC
Q
F
Q
G
(TOP VIEW)
Q
1
B
Q
2
C
Q
3
D
Q
4
E
5
Q
F
6
Q
G
7
Q
H
GND
8
(TOP VIEW)
CQB
Q
3212019
4
5
6
7
8
910111213
H
Q
NC
GND
NC
16
15
14
13
12
11
10
9
VCCQ
′
H
Q
V
CC
Q
A
SER
OE
RCLK
SRCLK
SRCLR
Q
H′
A
SER
18
OE
17
NC
16
RCLK
15
14
SRCLK
SRCLR
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54HC595, SN74HC595
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS041B – DECEMBER 1982 – REVISED MA Y 1997
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
†
13
OE
SER
12
10
11
14
RCLK C2
SRCLR
SRCLK
EN3
R
1D
SRG8
C1/
2D
2D
15
3
3
Q
A
1
Q
B
2
Q
C
3
Q
D
4
Q
E
5
Q
F
6
Q
G
7
Q
H
9
Q
H′
2
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logic diagram (positive logic)
13
OE
SER
12
10
11
14
RCLK
SRCLR
SRCLK
1D
R
C1
SN54HC595, SN74HC595
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS041B – DECEMBER 1982 – REVISED MA Y 1997
3R
C3
3S
15
Q
A
2S
2R
R
2S
2R
R
2S
2R
R
2S
2R
R
2S
2R
R
C2
C2
C2
C2
C2
3R
3S
3R
3S
3R
3S
3R
3S
3R
3S
C3
C3
C3
C3
C3
1
Q
B
2
Q
C
3
Q
D
4
Q
E
5
Q
F
Pin numbers shown are for the D, J, N, and W packages.
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2S
2R
R
2S
2R
R
C2
C2
3R
3S
3R
3S
C3
C3
6
Q
G
7
Q
H
9
Q
H′
3
SN54HC595, SN74HC595
UNIT
‡
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS041B – DECEMBER 1982 – REVISED MA Y 1997
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
†
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions
SN54HC595 SN74HC595
MIN NOM MAX MIN NOM MAX
V
V
V
V
V
t
t
T
‡
If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally ,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
Supply voltage 2 5 6 2 5 6 V
CC
VCC = 2 V 1.5 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
Input transition (rise and fall) time
Operating free-air temperature –55 125 –40 85 °C
A
VCC = 4.5 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
VCC = 4.5 V
VCC = 6 V 0 1.8 0 1.8
VCC = 2 V 0 1000 0 1000
VCC = 4.5 V
VCC = 6 V 0 400 0 400
3.15 3.15
0 1.35 0 1.35
CC
CC
0 500 0 500
0 V
0 V
CC
CC
V
V
V
V
ns
4
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PARAMETER
TEST CONDITIONS
V
UNIT
4.5 V
6 V
4.5 V
6 V
SN54HC595, SN74HC595
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS041B – DECEMBER 1982 – REVISED MA Y 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54HC595 SN74HC595
MIN TYP MAX MIN MAX MIN MAX
3.98 4.3 3.7 3.84
3.98 4.3 3.7 3.84
5.48 5.8 5.2 5.34
5.48 5.8 5.2 5.34
0.17 0.26 0.4 0.33
0.17 0.26 0.4 0.33
0.15 0.26 0.4 0.33
0.15 0.26 0.4 0.33
3 10 10 10 pF
V
V
V
V
I
I
I
C
OH
OL
I
OZ
CC
i
CC
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA
VI = VIH or V
VI = VIH or V
VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
VO = VCC or 0 6 V ±0.01 ±0.5 ±10 ±5 µA
VI = VCC or 0, IO = 0 6 V 8 160 80 µA
QH′, IOH = –4 mA
IL
QA–QH, IOH = –6 mA
QH′, IOH = –5.2 mA
QA–QH, IOH = –7.8 mA
IOL = 20 µA
QH′, IOL = 4 mA
IL
QA–QH, IOL = 6 mA
QH′, IOL = 5.2 mA
QA–QH, IOL = 7.8 mA
4.5 V 4.4 4.499 4.4 4.4
6 V 5.9 5.999 5.9 5.9
2 V 0.002 0.1 0.1 0.1
4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1
2 V
to 6 V
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5
SN54HC595, SN74HC595
V
UNIT
twPulse duration
ns
↑
↑
†
tsuSetup time
ns
↑
↑
↑
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS041B – DECEMBER 1982 – REVISED MA Y 1997
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C SN54HC595 SN74HC595
CC
MIN MAX MIN MAX MIN MAX
2 V 0 6 0 4.2 0 5
f
clock
t
h
†
This setup time ensures the output register sees stable data from the shift-register outputs. The clocks may be tied together, in which case the
output register is one clock pulse behind the shift register.
Clock frequency
SRCLK or RCLK high or low
SRCLR low
SER before SRCLK
SRCLK↑ before RCLK
p
SRCLR low before RCLK
SRCLR high (inactive) before SRCLK
Hold time, SER after SRCLK
4.5 V
6 V 0 36 0 25 0 29
2 V 80 120 100
4.5 V 16 24 20
6 V 14 20 17
2 V 80 120 100
4.5 V 16 24 20
6 V 14 20 17
2 V 100 150 125
4.5 V 20 30 25
6 V 17 25 21
2 V 75 113 94
4.5 V 15 23 19
6 V 13 19 16
2 V 50 75 65
4.5 V 10 15 13
6 V 9 13 11
2 V 50 75 60
4.5 V 10 15 12
6 V 9 13 11
2 V 0 0 0
4.5 V 0 0 0
6 V 0 0 0
0 31 0 21 0 25
MHz
ns
6
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PARAMETER
V
UNIT
t
ns
t
ns
PARAMETER
V
UNIT
SN54HC595, SN74HC595
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS041B – DECEMBER 1982 – REVISED MA Y 1997
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54HC595 SN74HC595
MIN TYP MAX MIN MAX MIN MAX
MHz
ns
ns
ns
f
max
pd
t
PHL
t
en
t
dis
t
FROM TO
(INPUT) (OUTPUT)
SRCLK Q
RCLK QA–Q
SRCLR Q
OE QA–Q
OE QA–Q
H′
H′
QA–Q
Q
H′
H
H
H
H
CC
2 V 6 26 4.2 5
4.5 V 31 38 21 25
6 V 36 42 25 29
2 V 50 160 240 200
4.5 V 17 32 48 40
6 V 14 27 41 34
2 V 50 150 225 187
4.5 V 17 30 45 37
6 V 14 26 38 32
2 V 51 175 261 219
4.5 V 18 35 52 44
6 V 15 30 44 37
2 V 40 150 225 187
4.5 V 15 30 45 37
6 V 13 26 38 32
2 V 42 200 300 250
4.5 V 23 40 60 50
6 V 20 34 51 43
2 V 28 60 90 75
4.5 V 8 12 18 15
6 V 6 10 15 13
2 V 28 75 110 95
4.5 V 8 15 22 19
6 V 6 13 19 16
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
FROM TO
(INPUT) (OUTPUT)
t
pd
t
en
t
t
RCLK QA–Q
OE QA–Q
QA–Q
H
H
H
CC
2 V 60 200 300 250
4.5 V 22 40 60 50
6 V 19 34 51 43
2 V 70 200 298 250
4.5 V 23 40 60 50
6 V 19 34 51 43
2 V 45 210 315 265
4.5 V 17 42 63 53
6 V 13 36 53 45
TA = 25°C SN54HC595 SN74HC595
MIN TYP MAX MIN MAX MIN MAX
ns
ns
ns
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance No load 400 pF
pd
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7
SN54HC595, SN74HC595
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS041B – DECEMBER 1982 – REVISED MA Y 1997
PARAMETER MEASUREMENT INFORMATION
V
S1
S2
V
50%
0 V
V
50%
0 V
From Output
Under Test
(see Note A)
High-Level
Pulse
Low-Level
Pulse
Test
Point
C
L
LOAD CIRCUIT
50%
50%
VOLTAGE WAVEFORMS
PULSE DURATIONS
R
L
t
w
CC
CC
CC
PARAMETER C
t
Data
t
PZH
t
PZL
t
PHZ
t
PLZ
t
en
t
dis
tpd or t
Reference
Input
Input
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
R
L
1 kΩ
1 kΩ
t
su
90% 90%
VOLTAGE WAVEFORMS
t
r
L
50 pF
or
150 pF
50 pF
50 pF
or
150 pF
50%
S1
Open Closed
Closed Open
Open Closed
Closed Open
Open Open––
t
h
50%50%
S2
V
CC
0 V
V
CC
10%10%
0 V
t
f
Input
In-Phase
Output
Out-of-
Phase
Output
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
50%
t
PLH
90% 90%
t
PHL
50% 50%
10% 10%
VOLTAGE WAVEFORMS
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. For clock inputs, f
E. The outputs are measured one at a time with one input transition per measurement.
F. t
G. t
H. t
PLZ
PZL
PLH
and t
and t
and t
max
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
50%
t
PHL
50%50%
t
r
t
PLH
t
f
is measured when the input duty cycle is 50%.
.
dis
V
CC
0 V
V
OH
10%10%
V
OL
t
f
V
OH
90%90%
V
OL
t
r
Output
Control
(Low-Level
Enabling)
t
PZL
Output
Waveform 1
(See Note B)
t
PZH
Output
Waveform 2
(See Note B)
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
50%
≈ V
CC
50%
50%
VOLTAGE WAVEFORMS
50%
t
PLZ
10%
90%
t
PHZ
V
CC
0 V
≈ V
V
OL
V
OH
≈ 0 V
CC
Figure 1. Load Circuit and Voltage Waveforms
8
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