SN54HC594, SN74HC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS040C – DECEMBER 1982 – REVISED FEBRUARY 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
8-Bit Serial-In, Parallel-Out Shift Registers
With Storage
D
Independent Direct Overriding Clears on
Shift and Storage Registers
D
Independent Clocks for Both Shift and
Storage Registers
D
High-Current Outputs Can Drive Up to
15 LSTTL Loads
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Ceramic Flat (W) Packages,
Ceramic Chip Carriers (FK), and Standard
Plastic (N) and Ceramic (J) 300-mil DIPs
description
The ’HC594 devices contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. Separate clocks and direct
overriding clear (RCLR
, SRCLR) inputs are
provided on both the shift and storage registers.
A serial (Q
H′
) output is provided for cascading
purposes.
Both the shift register (RCLK) and storage register
(SRCLK) clocks are positive edge triggered. If
both clocks are connected together, the shift
register is always one count pulse ahead of the
storage register.
The parallel (Q
A–QH
) outputs have high-current
capability. Q
H′
is a standard output.
The SN54HC594 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HC594 is characterized for operation from –40°C to 85°C.
Copyright 1998, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54HC594 ...J OR W PACKAGE
SN74HC594 . . . D, DB, OR N PACKAGE
(TOP VIEW)
SN54HC594 . . . FK PACKAGE
(TOP VIEW)
NC – No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
GND
V
CC
Q
A
SER
RCLR
RCLK
SRCLK
SRCLR
Q
H′
3212019
910111213
4
5
6
7
8
18
17
16
15
14
SER
RCLR
NC
RCLK
SRCLK
Q
D
Q
E
NC
Q
F
Q
G
Q
NC
SRCLR
H
GND
NC
CQB
VCCQ
A
Q
H
Q
′
SN54HC594, SN74HC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS040C – DECEMBER 1982 – REVISED FEBRUARY 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
R
10
15
3
1
2
3
11
SRCLK
R3
13
12
RCLK
C2
4
5
6
7
3
2D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, and W packages.
SRG8
RCLR
SRCLR
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
1D
14
SER
C1/
2D
9
Q
H′
SN54HC594, SN74HC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS040C – DECEMBER 1982 – REVISED FEBRUARY 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
R
3R
C3
3S
1D
C1
R
R
3R
C3
3S
2R
C2
R
2S
R
3R
C3
3S
2R
C2
R
2S
R
3R
C3
3S
2R
C2
R
2S
R
3R
C3
3S
2R
C2
R
2S
R
3R
C3
3S
2R
C2
R
2S
R
3R
C3
3S
2R
C2
R
2S
R
3R
C3
3S
2R
C2
R
2S
13
12
10
11
14
15
1
2
3
4
5
6
7
9
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
Q
H′
RCLR
SRCLR
RCLK
SRCLK
SER
Pin numbers shown are for the D, DB, J, N, and W packages.
SN54HC594, SN74HC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS040C – DECEMBER 1982 – REVISED FEBRUARY 1998
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range
†
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package 131°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions (see Note 3)
SN54HC594 SN74HC594
MIN NOM MAX MIN NOM MAX
UNIT
V
CC
Supply voltage 2 5 6 2 5 6 V
VCC = 2 V 1.5 1.5
V
IH
High-level input voltage
VCC = 4.5 V 3.15 3.15
V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
V
IL
Low-level input voltage
VCC = 4.5 V
0 1.35 0 1.35
V
VCC = 6 V 0 1.8 0 1.8
V
I
Input voltage 0 V
CC
0 V
CC
V
V
O
Output voltage 0 V
CC
0 V
CC
V
VCC = 2 V 0 1000 0 1000
t
t
Input transition (rise and fall) time
VCC = 4.5 V 0 500 0 500
ns
VCC = 6 V 0 400 0 400
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54HC594, SN74HC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS040C – DECEMBER 1982 – REVISED FEBRUARY 1998
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54HC594 SN74HC594
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA
4.5 V 4.4 4.499 4.4 4.4
6 V 5.9 5.999 5.9 5.9
V
OH
VI = VIH or V
IL
QH′, IOH = –4 mA
3.98 4.3 3.7 3.84
V
QA–QH, IOH = –6 mA
4.5 V
3.98 4.3 3.7 3.84
QH′, IOH = –5.2 mA
5.48 5.8 5.2 5.34
QA–QH, IOH = –7.8 mA
6 V
5.48 5.8 5.2 5.34
2 V 0.002 0.1 0.1 0.1
IOL = 20 µA
4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1
V
OL
VI = VIH or V
IL
QH′, IOL = 4 mA
0.17 0.26 0.4 0.33
V
QA–QH, IOL = 6 mA
4.5 V
0.17 0.26 0.4 0.33
QH′, IOL = 5.2 mA
0.15 0.26 0.4 0.33
QA–QH, IOL = 7.8 mA
6 V
0.15 0.26 0.4 0.33
I
I
VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
I
OZ
VO = VCC or 0 6 V ±0.01 ±0.5 ±10 ±5 µA
I
CC
VI = VCC or 0, IO = 0 6 V 8 160 80 µA
C
i
2 V
to 6 V
3 10 10 10 pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54HC594, SN74HC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS040C – DECEMBER 1982 – REVISED FEBRUARY 1998
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C SN54HC594 SN74HC594
V
CC
MIN MAX MIN MAX MIN MAX
UNIT
2 V 5 3.3 4
f
clock
Clock frequency
4.5 V
25 17 20
MHz
6 V 29 20 24
2 V 100 150 125
SRCLK or RCLK high or low
4.5 V 20 30 25
6 V 17 25 21
twPulse duration
2 V 100 150 125
ns
SRCLR or RCLR low
4.5 V 20 30 25
6 V 17 25 21
2 V 90 135 110
SER before SRCLK
↑
4.5 V 18 27 22
6 V 15 23 19
2 V 90 135 110
SRCLK↑ before RCLK
↑
†
4.5 V 18 27 22
6 V 15 23 19
2 V 50 75 63
t
su
Setup time SRCLR low before RCLK
↑
4.5 V 10 15 13
ns
6 V 9 13 11
2 V 20 20 20
SRCLR high (inactive) before SRCLK
↑
4.5 V 10 10 10
6 V 10 10 10
2 V 5 5 5
RCLR high (inactive) before SRCLK
↑
4.5 V 5 5 5
6 V 5 5 5
2 V 5 5 5
t
h
Hold time, SER after SRCLK
↑
4.5 V 5 5 5
ns
6 V 5 5 5
†
This setup time ensures the output register sees stable data from the shift-register outputs. The clocks may be tied together, in which case the
output register is one clock pulse behind the shift register.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54HC594, SN74HC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS040C – DECEMBER 1982 – REVISED FEBRUARY 1998
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
FROM TO
TA = 25°C SN54HC594 SN74HC594
PARAMETER
(INPUT) (OUTPUT)
V
CC
MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 5 8 3.3 4
f
max
4.5 V 25 35 17 20
MHz
6 V 29 40 20 24
2 V 50 150 225 185
SRCLK Q
H′
4.5 V 20 30 45 37
6 V 15 25 38 31
t
pd
2 V 50 150 225 185
ns
RCLK QA–Q
H
4.5 V 20 30 45 37
6 V 15 25 38 31
2 V 50 150 225 185
SRCLR Q
H′
4.5 V 20 30 45 37
6 V 15 25 38 31
t
PHL
2 V 50 125 185 155
ns
RCLR QA–Q
H
4.5 V 20 25 37 31
6 V 15 21 31 26
2 V 38 75 110 95
Q
H′
4.5 V 8 15 22 19
6 V 6 13 19 16
t
t
2 V 38 60 90 75
ns
QA–Q
H
4.5 V 8 12 18 15
6 V 6 10 15 13
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
FROM TO
TA = 25°C SN54HC594 SN74HC594
PARAMETER
(INPUT) (OUTPUT)
V
CC
MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 90 200 300 250
t
pd
RCLK QA–Q
H
4.5 V 23 40 60 50
ns
6 V 19 34 51 43
2 V 90 200 300 250
t
PHL
RCLR QA–Q
H
4.5 V 23 40 60 50
ns
6 V 19 34 51 43
2 V 45 210 315 265
t
t
QA–Q
H
4.5 V 17 42 63 53
ns
6 V 13 36 53 45
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
pd
Power dissipation capacitance No load 395 pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54HC594, SN74HC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS040C – DECEMBER 1982 – REVISED FEBRUARY 1998
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
t
h
t
su
50%
50%50%
10%10%
90% 90%
V
CC
V
CC
0 V
0 V
t
r
t
f
Reference
Input
Data
Input
50%
High-Level
Pulse
50%
V
CC
0 V
50%
50%
V
CC
0 V
t
w
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%50%
10%10%
90% 90%
V
CC
V
OH
V
OL
0 V
t
r
t
f
Input
In-Phase
Output
50%
t
PLH
t
PHL
50% 50%
10% 10%
90%90%
V
OH
V
OL
t
r
t
f
t
PHL
t
PLH
Out-of-Phase
Output
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, f
max
is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. t
PLH
and t
PHL
are the same as tpd.
F. tf and tr are the same as tt.
Test
Point
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT
Figure 1. Load Circuit and Voltage Waveforms
IMPORTANT NOTICE
T exas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor
product or service without notice, and advises its customers to obtain the latest version of relevant information
to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications applicable at
the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each
device is not necessarily performed, except those mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or
severe property or environmental damage (“Critical Applications”).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED
TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI
products in such applications requires the written approval of an appropriate TI officer. Questions concerning
potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license, either
express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which such semiconductor products
or services might be or are used.
Copyright 1998, Texas Instruments Incorporated
Loading...