Texas Instruments SN74HC590AD, SN74HC590ADR, SN74HC590ADW, SN74HC590ADWR, SN74HC590AN Datasheet
...
SN54HC590A, SN74HC590A
8-BIT BINARY COUNTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS039C – DECEMBER 1982 – REVISED MA Y 1997
D
8-Bit Counter With Register
D
High-Current 3-State Parallel Register
Outputs Can Drive up to 15 LSTTL Loads
D
Counter Has Direct Clear
D
Package Options Include Plastic
Small-Outline (D, DW), and Ceramic Flat
(W) Packages, Ceramic Chip Carriers (FK),
and Standard Plastic (N) and Ceramic (J)
300-mil DIPs
description
The ’HC590A contain an 8-bit binary counter that
feeds an 8-bit storage register. The storage
register has parallel outputs. Separate clocks are
provided for both the binary counter and storage
register. The binary counter features direct clear
(CCLR
ripple-carry output (RCO) is provided for
cascading. Expansion is easily accomplished for
two stages by connecting RCO
CCKEN of the second stage. Cascading for larger
count chains can be accomplished by connecting
RCO of each stage to the counter clock (CCLK)
input of the following stage.
Both CCLK and the register clock (RCLK) input
are positive-edge triggered. If both clocks are
connected together, the counter state is always
one count ahead of the register. Internal circuitry
prevents clocking from the clock enable.
) and count-enable (CCKEN) inputs. A
of the first stage to
SN54HC590A ...J OR W PACKAGE
SN74HC590A . . . D, DW, OR N PACKAGE
SN54HC590A . . . FK PACKAGE
Q
D
Q
E
NC
Q
F
Q
G
NC – No internal connection
(TOP VIEW)
Q
1
B
Q
2
C
Q
3
D
Q
4
E
5
Q
F
6
Q
G
7
Q
H
GND
8
(TOP VIEW)
CQB
Q
3212019
4
5
6
7
8
910111213
H
Q
NC
NC
GND
16
15
14
13
12
11
10
9
VCCQ
RCO
V
CC
Q
A
OE
RCLK
CCKEN
CCLK
CCLR
RCO
A
OE
18
RCLK
17
NC
16
CCKEN
15
14
CCLK
CCLR
The SN54HC590A is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HC590A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1997, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54HC590A, SN74HC590A
8-BIT BINARY COUNTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS039C – DECEMBER 1982 – REVISED MA Y 1997
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DW, J, N, and W packages.
†
14
OE
RCLK C2
CCKEN
CCLK 1+
CCLR
13
12
11
10
EN3
G1
CT = 0
CTR8
(CT = 255) Z4
2D 3
9
15
RCO
Q
A
1
Q
B
2
Q
C
3
Q
D
4
Q
E
5
Q
F
6
Q
G
7
Q
H
4
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
14
OE
RCLK
13
SN54HC590A, SN74HC590A
8-BIT BINARY COUNTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS039C – DECEMBER 1982 – REVISED MA Y 1997
CCKEN
CCLK
CCLR
12
11
10
9
RCO
15
T
R
T
R
T
R
T
R
1R
C1
1S
1R
C1
1S
1R
C1
1S
1R
C1
1S
Q
A
1
Q
B
2
Q
C
3
Q
D
T
R
T
R
T
R
T
R
Pin numbers shown are for the D, DW, J, N, and W packages.
1R
1S
1R
1S
1R
1S
1R
1S
C1
C1
C1
C1
4
Q
E
5
Q
F
6
Q
G
7
Q
H
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54HC590A, SN74HC590A
UNIT
‡
8-BIT BINARY COUNTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS039C – DECEMBER 1982 – REVISED MA Y 1997
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
†
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DW package 105°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions
SN54HC590A SN74HC590A
MIN NOM MAX MIN NOM MAX
V
V
V
V
V
t
t
T
‡
If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally ,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
Supply voltage 2 5 6 2 5 6 V
CC
VCC = 2 V 1.5 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
Input transition (rise and fall) time
Operating free-air temperature –55 125 –40 85 °C
A
VCC = 4.5 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
VCC = 4.5 V
VCC = 6 V 0 1.8 0 1.8
VCC = 2 V 0 1000 0 1000
VCC = 4.5 V
VCC = 6 V 0 400 0 400
3.15 3.15
0 1.35 0 1.35
CC
CC
0 500 0 500
0 V
0 V
CC
CC
V
V
V
V
ns
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
TEST CONDITIONS
V
UNIT
4.5 V
6 V
4.5 V
6 V
SN54HC590A, SN74HC590A
8-BIT BINARY COUNTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS039C – DECEMBER 1982 – REVISED MA Y 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54HC590A SN74HC590A
MIN TYP MAX MIN MAX MIN MAX
3.98 4.3 3.7 3.84
3.98 4.3 3.7 3.84
5.48 5.8 5.2 5.34
5.48 5.8 5.2 5.34
0.17 0.26 0.4 0.33
0.17 0.26 0.4 0.33
0.15 0.26 0.4 0.33
0.15 0.26 0.4 0.33
3 10 10 10 pF
V
V
V
V
I
I
I
C
OH
OL
I
OZ
CC
i
CC
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA
VI = VIH or V
VI = VIH or V
VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
VO = VCC or 0 6 V ±0.01 ±0.5 ±10 ±5 µA
VI = VCC or 0, IO = 0 6 V 8 160 80 µA
RCO, IOH = –4 mA
IL
QA–QH, IOH = –6 mA
RCO, IOH = –5.2 mA
QA–QH, IOH = –7.8 mA
IOL = 20 µA
RCO, IOL = 4 mA
IL
QA–QH, IOL = 6 mA
RCO, IOL = 5.2 mA
QA–QH, IOL = 7.8 mA
4.5 V 4.4 4.499 4.4 4.4
6 V 5.9 5.999 5.9 5.9
2 V 0.002 0.1 0.1 0.1
4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1
2 V
to 6 V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54HC590A, SN74HC590A
V
UNIT
twPulse duration
ns
↑
↑
↑
†
↑
8-BIT BINARY COUNTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS039C – DECEMBER 1982 – REVISED MA Y 1997
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C SN54HC590A SN74HC590A
CC
MIN MAX MIN MAX MIN MAX
2 V 0 4 0 2.5 0 3.2
f
clock
t
su
t
h
†
This setup time ensures that the register gets stable data from the counter outputs. The clocks may be tied together, in which case the register
is one clock pulse behind the counter.
Clock frequency
CCLK or RCLK high or low
CCLR low
CCKEN low before CCLK
Setup time CCLR high (inactive) before CCLK
CCLK↑ before RCLK
Hold time CCKEN low after CCLK
4.5 V
6 V 0 24 0 16 0 19
2 V 125 200 155
4.5 V 25 38 31
6 V 21 32 26
2 V 100 150 125
4.5 V 20 30 25
6 V 17 26 21
2 V 100 150 125
4.5 V 20 30 25
6 V 17 26 21
2 V 100 150 125
4.5 V 20 30 25
6 V 17 26 21
2 V 100 150 125
4.5 V 20 30 25
6 V 17 26 21
2 V 50 75 60
4.5 V 10 15 12
6 V 9 13 11
0 20 0 13 16
MHz
ns
ns
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
(INPUT)
(OUTPUT)
MIN
MAX
↑
↓
↑
↓
↑
t
ns
SN54HC590A, SN74HC590A
8-BIT BINARY COUNTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS039C – DECEMBER 1982 – REVISED MA Y 1997
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
f
max
t
pd
t
PLH
t
pd
t
en
t
dis
t
* This parameter is not production tested for the SN54HC590A.
FROM
CCLK
CCLR
RCLK
OE
OE
TO
RCO
RCO
Q
Q
Q
RCO
Q
V
CC
MIN TYP MAX
2 V 4 8 2.5
4.5 V 20 35 13
6 V 24 40 16
2 V 80 150 225
4.5 V 20 31 45
6 V 15 26 38
2 V 70 130 195
4.5 V 18 28 39
6 V 14 23 33
2 V 70 140 210
4.5 V 18 31 42
6 V 14 25 36
2 V 80 125 185
4.5 V 20 30 37
6 V 15 28 31
2 V 80 125 185
4.5 V 20 30 37
6 V 15 28 31
2 V 38 75 110
4.5 V 8 15 22
6 V 6 13 19
2 V 38 60 90
4.5 V 8 12 18
6 V 6 10 15
SN54HC590A
TA = 25°C
UNIT
MHz
ns
ns
ns
ns
ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN54HC590A, SN74HC590A
(INPUT)
(OUTPUT)
MIN
MAX
↑
↓
↑
↓
↑
t
ns
8-BIT BINARY COUNTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS039C – DECEMBER 1982 – REVISED MA Y 1997
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN74HC590A
TA = 25°C
UNIT
MHz
ns
ns
ns
ns
ns
PARAMETER
f
max
t
pd
t
PLH
t
pd
t
en
t
dis
t
FROM
CCLK
CCLR
RCLK
OE
OE
TO
RCO
RCO
Q
Q
Q
RCO
Q
V
CC
MIN TYP MAX
2 V 4 8 3.2
4.5 V 20 35 16
6 V 24 40 19
2 V 80 150 190
4.5 V 20 30 38
6 V 15 26 33
2 V 70 130 165
4.5 V 18 26 33
6 V 14 22 28
2 V 70 140 175
4.5 V 18 28 35
6 V 14 24 30
2 V 80 125 155
4.5 V 20 25 31
6 V 15 21 26
2 V 80 125 155
4.5 V 20 25 31
6 V 15 21 26
2 V 38 75 95
4.5 V 8 15 19
6 V 6 13 16
2 V 38 60 75
4.5 V 8 12 15
6 V 6 10 13
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
(INPUT)
(OUTPUT)
MIN
MAX
↑
*
(INPUT)
(OUTPUT)
MIN
MAX
↑
SN54HC590A, SN74HC590A
8-BIT BINARY COUNTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS039C – DECEMBER 1982 – REVISED MA Y 1997
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
t
pd
t
en
t
t
* This parameter is not production tested for the SN54HC590A.
FROM
RCLK
OE Q
TO
Q
Q
V
CC
MIN TYP MAX
2 V 100 300 447
4.5 V 24 60 90
6 V 20 51 77
2 V 90 200 300
4.5 V 23 40 60
6 V 19 34 51
2 V 45 210 315
4.5 V 17 42 63
6 V 13 36 53
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
t
pd
t
en
t
t
FROM
RCLK
OE Q
TO
Q
Q
V
CC
MIN TYP MAX
2 V 100 300 380
4.5 V 24 60 76
6 V 20 51 65
2 V 90 200 250
4.5 V 23 40 50
6 V 19 34 43
2 V 45 210 265
4.5 V 17 42 53
6 V 13 36 45
SN54HC590A
TA = 25°C
SN74HC590A
TA = 25°C
UNIT
ns
ns
ns
UNIT
ns
ns
ns
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance No load 250 pF
pd
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
SN54HC590A, SN74HC590A
8-BIT BINARY COUNTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS039C – DECEMBER 1982 – REVISED MA Y 1997
PARAMETER MEASUREMENT INFORMATION
V
S1
S2
V
50%
0 V
V
50%
0 V
From Output
Under Test
(see Note A)
High-Level
Pulse
Low-Level
Pulse
Test
Point
C
L
LOAD CIRCUIT
50%
50%
VOLTAGE WAVEFORMS
PULSE DURATIONS
R
L
t
w
CC
CC
CC
PARAMETER C
t
Data
t
PZH
t
PZL
t
PHZ
t
PLZ
t
en
t
dis
tpd or t
Reference
Input
Input
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
R
L
1 kΩ
1 kΩ
t
su
90% 90%
VOLTAGE WAVEFORMS
t
r
L
50 pF
or
150 pF
50 pF
50 pF
or
150 pF
50%
S1
Open Closed
Closed Open
Open Closed
Closed Open
Open Open––
t
h
50%50%
S2
V
CC
0 V
V
CC
10%10%
0 V
t
f
Input
In-Phase
Output
Out-of-
Phase
Output
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
50%
t
PLH
90% 90%
t
PHL
50% 50%
10% 10%
VOLTAGE WAVEFORMS
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. For clock inputs, f
E. The outputs are measured one at a time with one input transition per measurement.
F. t
G. t
H. t
PLZ
PZL
PLH
and t
and t
and t
max
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
50%
t
PHL
50%50%
t
r
t
PLH
t
f
is measured when the input duty cycle is 50%.
.
dis
V
CC
0 V
V
OH
10%10%
V
OL
t
f
V
OH
90%90%
V
OL
t
r
Output
Control
(Low-Level
Enabling)
t
PZL
Output
Waveform 1
(See Note B)
t
PZH
Output
Waveform 2
(See Note B)
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
50%
≈ V
CC
50%
50%
VOLTAGE WAVEFORMS
50%
t
PLZ
10%
90%
t
PHZ
V
CC
0 V
≈ V
V
OL
V
OH
≈ 0 V
CC
10
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 1998, Texas Instruments Incorporated
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