Datasheet JM38510-65406BRA, SN54HC573AJ, SN74HC573ADW, SN74HC573ADWR, SN74HC573AN Datasheet (Texas Instruments)
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SN54HC573A, SN74HC573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS147B – DECEMBER 1982 – REVISED MA Y 1997
D
High-Current 3-State Outputs Drive Bus
Lines Directly or up to 15 LSTTL Loads
D
Bus-Structured Pinout
D
Package Options Include Plastic
Small-Outline (DW) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
description
These octal transparent D-type latches feature
3-state outputs designed specifically for driving
highly capacitive or relatively low-impedance
loads. They are particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the
Q outputs respond to the data (D) inputs. When
LE is low, the outputs are latched to retain the data
that was set up.
A buffered output-enable (OE
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without interface or pullup components.
) input can be used
SN54HC573A ...J OR W PACKAGE
SN74HC573A . . . DW OR N PACKAGE
SN54HC573A . . . FK PACKAGE
3D
4D
5D
6D
7D
(TOP VIEW)
OE
1
1D
2
2D
3
3D
4
4D
5
5D
6
6D
7
7D
8
8D
9
GND
10
(TOP VIEW)
2D1DOE
3212019
4
5
6
7
8
910111213
8D
LE
20
19
18
17
16
15
14
13
12
11
CC
V
8Q
V
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
1Q
18
17
16
15
14
7Q
CC
2Q
3Q
4Q
5Q
6Q
GND
OE
does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN54HC573A is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HC573A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each latch)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
INPUTS
OE LE D
L H H H
L HL L
L LX Q
H X X Z
OUTPUT
Q
0
Copyright 1997, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54HC573A, SN74HC573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS147B – DECEMBER 1982 – REVISED MA Y 1997
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
OE
LE
1D
2D
3D
4D
5D
6D
7D
8D
1
11
2
3
4
5
6
7
8
9
EN
C1
1D
logic diagram (positive logic)
1
OE
11
LE
19
18
17
16
15
14
13
12
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
C1
1D
2
To Seven Other Channels
1D
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
19
1Q
‡
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
2
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UNIT
PARAMETER
TEST CONDITIONS
V
UNIT
recommended operating conditions
V
V
V
V
V
t
t
T
Supply voltage 2 5 6 2 5 6 V
CC
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
Input transition (rise and fall) time
Operating free-air temperature –55 125 –40 85 °C
A
SN54HC573A, SN74HC573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS147B – DECEMBER 1982 – REVISED MA Y 1997
SN54HC573A SN74HC573A
MIN NOM MAX MIN NOM MAX
VCC = 2 V 1.5 1.5
VCC = 4.5 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
VCC = 4.5 V
VCC = 6 V 0 1.8 0 1.8
VCC = 2 V 0 1000 0 1000
VCC = 4.5 V
VCC = 6 V 0 400 0 400
3.15 3.15
0 1.35 0 1.35
CC
CC
0 500 0 500
0 V
0 V
CC
CC
V
V
V
V
ns
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54HC573A SN74HC573A
MIN TYP MAX MIN MAX MIN MAX
V
V
V
V
I
I
I
C
OH
OL
I
OZ
CC
i
CC
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA
VI = VIH or V
VI = VIH or V
VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
VO = VCC or 0 6 V ±0.01 ±0.5 ±10 ±5 µA
VI = VCC or 0, IO = 0 6 V 8 160 80 µA
IL
IOH = –6 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –7.8 mA 6 V 5.48 5.8 5.2 5.34
IOL = 20 µA
IL
IOL = 6 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 7.8 mA 6 V 0.15 0.26 0.4 0.33
4.5 V 4.4 4.499 4.4 4.4
6 V 5.9 5.999 5.9 5.9
2 V 0.002 0.1 0.1 0.1
4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1
2 V to 6 V 3 10 10 10 pF
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3
SN54HC573A, SN74HC573A
V
UNIT
↓
↓
PARAMETER
V
UNIT
t
ns
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS147B – DECEMBER 1982 – REVISED MA Y 1997
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C SN54HC573A SN74HC573A
CC
MIN MAX MIN MAX MIN MAX
2 V 80 120 100
t
w
t
su
t
h
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
Pulse duration, LE high
Setup time, data before LE
Hold time, data after LE
FROM TO
(INPUT) (OUTPUT)
pd
t
en
t
dis
t
t
D Q
LE Any Q
OE Any Q
OE Any Q
Any Q
4.5 V
6 V 14 20 17
2 V 50 75 63
4.5 V 10 15 13
6 V 9 13 11
2 V 20 24 24
4.5 V 5 5 5
6 V 5 5 5
CC
MIN TYP MAX MIN MAX MIN MAX
2 V 77 175 265 220
4.5 V 26 35 53 44
6 V 23 30 45 38
2 V 87 175 265 220
4.5 V 27 35 53 44
6 V 23 30 45 38
2 V 68 150 225 190
4.5 V 24 30 45 38
6 V 21 26 38 32
2 V 47 150 225 190
4.5 V 23 30 45 38
6 V 21 26 38 32
2 V 28 60 90 75
4.5 V 8 12 18 15
6 V 6 10 15 13
16 24 20
TA = 25°C SN54HC573A SN74HC573A
ns
ns
ns
ns
ns
ns
4
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PARAMETER
V
UNIT
t
ns
SN54HC573A, SN74HC573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS147B – DECEMBER 1982 – REVISED MA Y 1997
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
FROM TO
(INPUT) (OUTPUT)
D Q
pd
LE Any Q
t
en
t
t
OE Any Q
Any Q
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance per latch No load 50 pF
pd
CC
2 V 95 200 300 250
4.5 V 33 40 60 50
6 V 21 34 51 43
2 V 103 225 335 285
4.5 V 33 45 67 57
6 V 29 38 57 48
2 V 85 200 300 250
4.5 V 29 40 60 50
6 V 26 34 51 43
2 V 60 210 315 265
4.5 V 17 42 63 53
6 V 14 36 53 45
TA = 25°C SN54HC573A SN74HC573A
MIN TYP MAX MIN MAX MIN MAX
ns
ns
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5
SN54HC573A, SN74HC573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS147B – DECEMBER 1982 – REVISED MA Y 1997
PARAMETER MEASUREMENT INFORMATION
V
CC
50%
50%
S1
S2
V
0 V
V
0 V
CC
CC
From Output
Under Test
(see Note A)
High-Level
Pulse
Low-Level
Pulse
Test
Point
C
L
LOAD CIRCUIT
50%
50%
VOLTAGE WAVEFORMS
PULSE DURATIONS
R
L
t
w
PARAMETER C
t
Data
t
PZH
t
PZL
t
PHZ
t
PLZ
t
en
t
dis
tpd or t
Reference
Input
Input
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
R
L
1 kΩ
1 kΩ
t
su
90% 90%
VOLTAGE WAVEFORMS
t
r
L
50 pF
or
150 pF
50 pF
50 pF
or
150 pF
50%
S1
Open Closed
Closed Open
Open Closed
Closed Open
Open Open––
t
h
S2
V
CC
0 V
V
50%50%
CC
10%10%
0 V
t
f
Input
In-Phase
Output
Out-of-
Phase
Output
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
50%
t
PLH
90% 90%
t
PHL
50% 50%
10% 10%
VOLTAGE WAVEFORMS
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. t
F. t
G. t
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
50%
t
PHL
50%50%
t
r
t
PLH
t
f
.
dis
Figure 1. Load Circuit and Voltage Waveforms
V
CC
0 V
V
OH
10%10%
V
OL
t
f
V
OH
90%90%
V
OL
t
r
Output
Control
(Low-Level
Enabling)
t
PZL
Output
Waveform 1
(See Note B)
t
PZH
Output
Waveform 2
(See Note B)
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
50%
≈ V
CC
50%
50%
VOLTAGE WAVEFORMS
50%
t
PLZ
10%
90%
t
PHZ
V
CC
0 V
≈ V
V
OL
V
OH
≈ 0 V
CC
6
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