Low On-State Impedance —
Typically, 50 Ω at VCC = 6 V
D
Individual Switch Controls
D
Extremely Low Input Current
D
Package Options Include Plastic
Small-Outline (D), Plastic Shrink
D, DB, PW, OR N PACKAGE
(TOP VIEW)
1A
1B
2B
2A
2C
3C
GND
1
2
3
4
5
6
7
14
13
12
11
10
V
CC
1C
4C
4A
4B
3B
9
3A
8
Small-Outline (DB), and Thin Shrink
Small-Outline (PW) Packages, and
Standard Plastic (N) 300-mil DIPs
description
The SN74HC4066 is a silicon-gate CMOS quadruple analog switch designed to handle both analog and digital
signals. Each switch permits signals with amplitudes of up to 6 V (peak) to be transmitted in either direction.
Each switch section has its own enable input control (C). A high-level voltage applied to C turns on the
associated switch section.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
The SN74HC4066 is characterized for operation from –40_C to 85_C.
FUNCTION TABLE
(each switch)
INPUT
CONTROL
(C)
LOFF
HON
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
1C
1A
2C
2A
3C
3A
4C
4A
13
1
5
4
6
8
12
11
X1
1
SWITCH
1
10
2
1B
3
2B
9
3B
4B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325B – MARCH 1996 – REVISED MA Y 1997
logic diagram, each switch (positive logic)
C
One of Four Switches
A
V
V
CC
CC
B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital signals
be transmitted at these low supply voltages.