Texas Instruments SN54HC4040J, SN74HC4040D, SN74HC4040DBLE, SN74HC4040DBR, SN74HC4040DR Datasheet
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SN54HC4040, SN74HC4040
12-BIT ASYNCHRONOUS BINARY COUNTERS
SCLS160B – DECEMBER 1982 – REVISED MA Y 1997
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
The ’HC4040 are 12-stage asynchronous binary
counters with the outputs of all stages available
externally. A high level at the clear (CLR) input
asynchronously clears the counter and resets all
outputs low. The count is advanced on a
high-to-low transition at the clock (CLK) input.
Applications include time-delay circuits, counter
controls, and frequency-dividing circuits.
The SN54HC4040 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC4040 is characterized for
operation from –40°C to 85°C.
11
10
†
RCTR12
0
CT=0
CT
11
logic symbol
CLR
CLK
13
12
14
15
SN54HC4040 . . . J OR W PACKAGE
SN74HC4040 . . . D, DB, N, OR PW PACKAGE
SN54HC4040 . . . FK PACKAGE
Q
E
Q
G
NC
Q
D
Q
C
9
Q
A
7
Q
B
6
Q
C
5
Q
D
3
Q
E
2
Q
F
4
Q
G
Q
H
Q
I
Q
J
Q
K
1
Q
L
NC – No internal connection
(TOP VIEW)
Q
1
L
Q
2
F
Q
3
E
Q
4
G
5
Q
D
6
Q
C
7
Q
B
GND
8
(TOP VIEW)
F
QQNC
3212019
4
5
6
7
8
910111213
B
Q
L
GND
NC
16
15
14
13
12
11
10
9
CC
V
A
Q
V
CC
Q
K
Q
J
Q
H
Q
I
CLR
CLK
Q
A
K
Q
18
17
16
15
14
CLK
Q
J
Q
H
NC
Q
I
CLR
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54HC4040, SN74HC4040
12-BIT ASYNCHRONOUS BINARY COUNTERS
SCLS160B – DECEMBER 1982 – REVISED MA Y 1997
logic diagram (positive logic)
11
CLR
10
CLK
R
T
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
R
T
2 4 13 12 14 15 1
Q
F
R
T
R
T
Q
G
absolute maximum ratings over operating free-air temperature range
R
T
953
Q
A
R
T
Q
H
R
T
7
Q
B
R
T
Q
I
R
T
6
Q
C
R
T
Q
J
R
T
Q
D
R
Q
K
Q
E
T
Q
L
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
(VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DB package 131°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 149°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
2
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UNIT
†
PARAMETER
TEST CONDITIONS
V
UNIT
SN54HC4040, SN74HC4040
12-BIT ASYNCHRONOUS BINARY COUNTERS
SCLS160B – DECEMBER 1982 – REVISED MA Y 1997
recommended operating conditions
SN54HC4040 SN74HC4040
MIN NOM MAX MIN NOM MAX
V
V
V
V
V
t
t
T
†
If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally ,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
Supply voltage 2 5 6 2 5 6 V
CC
VCC = 2 V 1.5 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
Input transition (rise and fall) time
Operating free-air temperature –55 125 –40 85 °C
A
VCC = 4.5 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
VCC = 4.5 V
VCC = 6 V 0 1.8 0 1.8
VCC = 2 V 0 1000 0 1000
VCC = 4.5 V
VCC = 6 V 0 400 0 400
3.15 3.15
0 1.35 0 1.35
CC
CC
0 500 0 500
0 V
0 V
CC
CC
V
V
V
V
ns
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54HC4040 SN74HC4040
MIN TYP MAX MIN MAX MIN MAX
V
V
V
V
I
I
C
OH
OL
I
CC
i
CC
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA
VI = VIH or V
VI = VIH or V
VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
VI = VCC or 0, IO = 0 6 V 8 160 80 µA
IL
IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –5.2 mA 6 V 5.48 5.8 5.2 5.34
IOL = 20 µA
IL
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33
4.5 V 4.4 4.499 4.4 4.4
6 V 5.9 5.999 5.9 5.9
2 V 0.002 0.1 0.1 0.1
4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1
2 V to 6 V 3 10 10 10 pF
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3
SN54HC4040, SN74HC4040
V
UNIT
twPulse duration
ns
↓
PARAMETER
V
UNIT
12-BIT ASYNCHRONOUS BINARY COUNTERS
SCLS160B – DECEMBER 1982 – REVISED MA Y 1997
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C SN54HC4040 SN74HC4040
CC
MIN MAX MIN MAX MIN MAX
2 V 0 5.5 0 3.7 0 4.3
f
clock
t
su
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
Clock frequency
Setup time, CLR inactive before CLK
FROM TO
(INPUT) (OUTPUT)
f
max
t
pd
t
PHL
t
t
CLK Q
CLR Any
CLK high or low
CLR high
A
Any
4.5 V
6 V 0 33 0 22 0 25
2 V 90 135 115
4.5 V 18 27 23
6 V 15 23 20
2 V 70 105 90
4.5 V 14 21 18
6 V 12 18 15
2 V 60 90 75
4.5 V 12 18 15
6 V 10 15 13
CC
MIN TYP MAX MIN MAX MIN MAX
2 V 5.5 10 3.7 4.3
4.5 V 28 45 19 22
6 V 33 53 22 25
2 V 62 150 225 190
4.5 V 16 30 45 38
6 V 12 26 38 32
2 V 63 140 210 175
4.5 V 17 28 42 35
6 V 13 24 36 30
2 V 28 75 110 95
4.5 V 8 15 22 19
6 V 6 13 19 16
0 28 0 19 0 22
TA = 25°C SN54HC4040 SN74HC4040
MHz
ns
MHz
ns
ns
ns
operating characteristics, TA = 25°C
4
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance No load 88 pF
pd
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50%
Test
Point
CL = 50 pF
(see Note A)
t
h
50%50%
From Output
Under Test
LOAD CIRCUIT
Reference
Input
t
su
Data
Input
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
90% 90%
t
r
VOLTAGE WAVEFORMS
SN54HC4040, SN74HC4040
12-BIT ASYNCHRONOUS BINARY COUNTERS
SCLS160B – DECEMBER 1982 – REVISED MA Y 1997
V
0 V
V
0 V
CC
CC
V
CC
0 V
V
50%50%
OH
10%10%
V
OL
t
f
V
OH
90%90%
V
OL
t
r
High-Level
Pulse
Low-Level
Pulse
Input
V
CC
0 V
V
CC
10%10%
0 V
t
f
In-Phase
Output
Out-of-Phase
Output
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
t
t
PLH
PHL
50%
t
w
50%
VOLTAGE WAVEFORMS
PULSE DURATIONS
90% 90%
t
r
50% 50%
10% 10%
t
f
VOLTAGE WAVEFORMS
50%
t
50%
50%
t
PHL
PLH
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, f
D. The outputs are measured one at a time with one input transition per measurement.
E. t
PLH
and t
PHL
is measured when the input duty cycle is 50%.
max
are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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5
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