Texas Instruments SN74HC4020N, SN74HC4020N3, SNJ54HC4020FK Datasheet
SN54HC4020, SN74HC4020
14-BIT ASYNCHRONOUS BINARY COUNTERS
SCLS158C – DECEMBER 1982 – REVISED FEBRUARY 2000
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) DIPs
description
These devices are 14-stage binary ripple-carry
counters that advance on the negative-going
edge of the clock pulse. The counters are reset to
zero (all outputs low) independently of the clock
(CLK) input when the clear (CLR) input goes high.
The SN54HC4020 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC4020 is characterized for
operation from –40°C to 85°C.
logic symbol
11
CLR
10
CLK
†
RCTR14
0
3
4
CT=0
CT
13
13
12
14
15
SN54HC4020 ...J OR W PACKAGE
SN74HC4020 . . . D, DB, N, OR PW PACKAGE
SN54HC4020 . . . FK PACKAGE
Q
N
Q
F
NC
Q
9
Q
A
7
Q
D
5
Q
E
4
Q
F
6
Q
G
Q
H
Q
I
Q
J
Q
K
1
Q
L
2
Q
M
3
Q
N
E
Q
G
NC – No internal connection
(TOP VIEW)
Q
1
L
Q
2
M
Q
3
N
Q
4
F
5
Q
E
6
Q
G
7
Q
D
GND
8
(TOP VIEW)
M
QQNC
3212019
4
5
6
7
8
910111213
D
Q
L
GND
NC
16
15
14
13
12
11
10
9
CC
V
A
Q
V
CC
Q
K
Q
J
Q
H
Q
I
CLR
CLK
Q
A
K
Q
18
17
16
15
14
CLK
Q
J
Q
H
NC
Q
I
CLR
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N,
PW, and W packages.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
SN54HC4020, SN74HC4020
14-BIT ASYNCHRONOUS BINARY COUNTERS
SCLS158C – DECEMBER 1982 – REVISED FEBRUARY 2000
logic diagram (positive logic)
11
CLR
10
CLK
R
T
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
R
T
613121415 1 2 3
Q
G
R
T
R
T
Q
H
absolute maximum ratings over operating free-air temperature range
R
T
9754
Q
A
R
T
Q
I
R
T
R
T
Q
J
R
T
R
T
Q
K
R
T
Q
D
R
T
Q
L
R
T
Q
E
Q
M
Q
F
R
T
Q
N
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
(VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DB package 82°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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