SN54HC4020, SN74HC4020
14-BIT ASYNCHRONOUS BINARY COUNTERS
SCLS158C – DECEMBER 1982 – REVISED FEBRUARY 2000
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) DIPs
description
These devices are 14-stage binary ripple-carry
counters that advance on the negative-going
edge of the clock pulse. The counters are reset to
zero (all outputs low) independently of the clock
(CLK) input when the clear (CLR) input goes high.
The SN54HC4020 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC4020 is characterized for
operation from –40°C to 85°C.
logic symbol
11
CLR
10
CLK
†
RCTR14
0
3
4
CT=0
CT
13
13
12
14
15
SN54HC4020 ...J OR W PACKAGE
SN74HC4020 . . . D, DB, N, OR PW PACKAGE
SN54HC4020 . . . FK PACKAGE
Q
N
Q
F
NC
Q
9
Q
A
7
Q
D
5
Q
E
4
Q
F
6
Q
G
Q
H
Q
I
Q
J
Q
K
1
Q
L
2
Q
M
3
Q
N
E
Q
G
NC – No internal connection
(TOP VIEW)
Q
1
L
Q
2
M
Q
3
N
Q
4
F
5
Q
E
6
Q
G
7
Q
D
GND
8
(TOP VIEW)
M
QQNC
3212019
4
5
6
7
8
910111213
D
Q
L
GND
NC
16
15
14
13
12
11
10
9
CC
V
A
Q
V
CC
Q
K
Q
J
Q
H
Q
I
CLR
CLK
Q
A
K
Q
18
17
16
15
14
CLK
Q
J
Q
H
NC
Q
I
CLR
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N,
PW, and W packages.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
SN54HC4020, SN74HC4020
14-BIT ASYNCHRONOUS BINARY COUNTERS
SCLS158C – DECEMBER 1982 – REVISED FEBRUARY 2000
logic diagram (positive logic)
11
CLR
10
CLK
R
T
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
R
T
613121415 1 2 3
Q
G
R
T
R
T
Q
H
absolute maximum ratings over operating free-air temperature range
R
T
9754
Q
A
R
T
Q
I
R
T
R
T
Q
J
R
T
R
T
Q
K
R
T
Q
D
R
T
Q
L
R
T
Q
E
Q
M
Q
F
R
T
Q
N
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
(VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DB package 82°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
PARAMETER
TEST CONDITIONS
V
UNIT
SN54HC4020, SN74HC4020
14-BIT ASYNCHRONOUS BINARY COUNTERS
SCLS158C – DECEMBER 1982 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 3)
SN54HC4020 SN74HC4020
MIN NOM MAX MIN NOM MAX
V
Supply voltage 2 5 6 2 5 6 V
CC
VCC = 2 V 1.5 1.5
V
High-level input voltage
IH
V
Low-level input voltage
IL
V
Input voltage 0 V
I
V
Output voltage 0 V
O
t
Input transition (rise and fall) time
t
T
Operating free-air temperature –55 125 –40 85 °C
A
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
VCC = 4.5 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
VCC = 4.5 V
VCC = 6 V 0 1.8 0 1.8
VCC = 2 V 0 1000 0 1000
VCC = 4.5 V
VCC = 6 V 0 400 0 400
, literature number SCBA004.
3.15 3.15
0 1.35 0 1.35
CC
CC
0 500 0 500
0 V
0 V
CC
CC
V
V
V
V
ns
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54HC4020 SN74HC4020
MIN TYP MAX MIN MAX MIN MAX
V
V
V
V
I
I
C
OH
OL
I
CC
i
CC
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA
VI = VIH or V
VI = VIH or V
VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
VI = VCC or 0, IO = 0 6 V 8 160 80 µA
IL
IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –5.2 mA 6 V 5.48 5.8 5.2 5.34
IOL = 20 µA
IL
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33
4.5 V 4.4 4.499 4.4 4.4
6 V 5.9 5.999 5.9 5.9
2 V 0.002 0.1 0.1 0.1
4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1
2 V to 6 V 3 10 10 10 pF
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54HC4020, SN74HC4020
V
UNIT
twPulse duration
ns
↓
PARAMETER
V
UNIT
14-BIT ASYNCHRONOUS BINARY COUNTERS
SCLS158C – DECEMBER 1982 – REVISED FEBRUARY 2000
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C SN54HC4020 SN74HC4020
CC
MIN MAX MIN MAX MIN MAX
2 V 0 5.5 0 3.7 0 4.3
f
clock
t
su
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
Clock frequency
Setup time, CLR inactive before CLK
FROM TO
(INPUT) (OUTPUT)
f
max
t
pd
t
PHL
t
t
CLK Q
CLR Any
CLK high or low
CLR high
A
Any
4.5 V
6 V 0 33 0 22 0 25
2 V 90 135 115
4.5 V 18 27 23
6 V 15 23 20
2 V 70 105 90
4.5 V 14 21 18
6 V 12 18 25
2 V 60 90 75
4.5 V 12 18 15
6 V 10 15 13
CC
2 V 5.5 10 3.7 4.3
4.5 V 28 45 19 22
6 V 33 53 22 25
2 V 62 150 225 190
4.5 V 16 30 45 38
6 V 12 26 38 32
2 V 63 140 210 175
4.5 V 17 28 42 35
6 V 13 24 36 30
2 V 28 75 110 95
4.5 V 8 15 22 19
6 V 6 13 19 16
MIN TYP MAX MIN MAX MIN MAX
0 28 0 19 0 22
TA = 25°C SN54HC4020 SN74HC4020
MHz
ns
MHz
ns
ns
ns
operating characteristics, TA = 25°C
4
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance No load 88 pF
pd
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC4020, SN74HC4020
14-BIT ASYNCHRONOUS BINARY COUNTERS
SCLS158C – DECEMBER 1982 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
t
r
t
f
Test
Point
CL = 50 pF
(see Note A)
50%
t
PHL
t
PLH
From Output
Under Test
LOAD CIRCUIT
Input
In-Phase
Output
Out-of-Phase
Output
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, f
D. The outputs are measured one at a time with one input transition per measurement.
E. t
PLH
and t
50%
t
PLH
90% 90%
t
PHL
50% 50%
10% 10%
VOLTAGE WAVEFORMS
is measured when the input duty cycle is 50%.
max
are the same as tpd.
PHL
V
Reference
Input
t
su
Data
Input
V
CC
0 V
V
50%50%
OH
10%10%
V
OL
t
f
V
OH
90%90%
V
OL
t
r
SETUP AND INPUT RISE AND FALL TIMES
High-Level
Low-Level
90% 90%
VOLTAGE WAVEFORMS
Pulse
Pulse
50%
t
r
50%
t
w
50%
VOLTAGE WAVEFORMS
PULSE DURATIONS
50%
50%
50%50%
CC
0 V
V
CC
10%10%
0 V
t
f
V
CC
0 V
V
CC
0 V
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
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