Texas Instruments SN54HC377J, SN74HC377DW, SN74HC377DWR, SN74HC377N, SNJ54HC377FK Datasheet
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SN54HC377, SN74HC377
OCTAL D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCLS307A – JANUARY 1996 – REVISED MA Y 1997
D
Eight Flip-Flops With Single-Rail Outputs
D
Clock Enable Latched to Avoid False
Clocking
D
Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators
D
Package Options Include Plastic
Small-Outline (DW) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
description
These devices are positive-edge-triggered octal
D-type flip-flops with an enable input. The ’HC377
are similar to the ’HC273 but feature a latched
clock-enable (CLKEN) input instead of a common
clear.
Information at the data (D) inputs meeting the
setup time requirements is transferred to the
Q outputs on the positive-going edge of the clock
(CLK) pulse if CLKEN
occurs at a particular voltage level and is not
directly related to the transition time of the
positive-going pulse. When CLK is at either the
high or low level, the D input has no effect at the
output. These devices are designed to prevent
false clocking by transitions at CLKEN
is low. Clock triggering
SN54HC377 ...J OR W PACKAGE
SN74HC377 . . . DW OR N PACKAGE
CLKEN
SN54HC377 . . . FK PACKAGE
2D
2Q
3Q
3D
4D
(TOP VIEW)
1
1Q
2
1D
3
2D
4
2Q
5
3Q
6
3D
7
4D
8
4Q
9
GND
10
(TOP VIEW)
1D1QCLKEN
3212019
4
5
6
7
8
910111213
4Q
GND
20
19
18
17
16
15
14
13
12
11
CLK
CC
V
5Q
V
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
8Q
18
17
16
15
14
5D
CC
8D
7D
7Q
6Q
6D
.
The SN54HC377 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HC377 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
INPUTS
CLKEN CLK D
H X X Q
L ↑ HH
L ↑ LL
X L X Q
OUTPUT
Q
0
0
Copyright 1997, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54HC377, SN74HC377
OCTAL D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCLS307A – JANUARY 1996 – REVISED MA Y 1997
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
CLKEN
CLK
1D
2D
3D
4D
5D
6D
7D
8D
1
11
3
4
7
8
13
14
17
18
G1
1C2
2D
12
15
16
19
2
1Q
5
2Q
6
3Q
9
4Q
5Q
6Q
7Q
8Q
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
SN54HC377, SN74HC377
OCTAL D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCLS307A – JANUARY 1996 – REVISED MA Y 1997
CLKEN
CLK
1D
2D
3D
4D
1
11
3
4
7
8
C1
1D
C1
1D
C1
1D
C1
1D
2
1Q
5
2Q
6
3Q
9
4Q
5D
6D
7D
8D
13
14
17
18
1D
1D
1D
1D
C1
C1
C1
C1
12
15
16
19
5Q
6Q
7Q
8Q
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54HC377, SN74HC377
UNIT
OCTAL D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCLS307A – JANUARY 1996 – REVISED MA Y 1997
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
†
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions
SN54HC377 SN74HC377
MIN NOM MAX MIN NOM MAX
V
V
V
V
V
t
t
T
Supply voltage 2 5 6 2 5 6 V
CC
VCC = 2 V 1.5 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
Input transition (rise and fall) time
Operating free-air temperature –55 125 –40 85 °C
A
VCC = 4.5 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
VCC = 4.5 V
VCC = 6 V 0 1.8 0 1.8
VCC = 2 V 0 1000 0 1000
VCC = 4.5 V
VCC = 6 V 0 400 0 400
3.15 3.15
0 1.35 0 1.35
CC
CC
0 500 0 500
0 V
0 V
CC
CC
V
V
V
V
ns
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
TEST CONDITIONS
V
UNIT
V
UNIT
tsuSetup time before CLK↑
ns
↑
SN54HC377, SN74HC377
OCTAL D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCLS307A – JANUARY 1996 – REVISED MA Y 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54HC377 SN74HC377
MIN TYP MAX MIN MAX MIN MAX
V
V
V
V
I
I
C
OH
OL
I
CC
i
CC
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA
VI = VIH or V
VI = VIH or V
VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
VI = VCC or 0, IO = 0 6 V 8 160 80 µA
IL
IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –5.2 mA 6 V 5.48 5.8 5.2 5.34
IOL = 20 µA
IL
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33
4.5 V 4.4 4.499 4.4 4.4
6 V 5.9 5.999 5.9 5.9
2 V 0.002 0.1 0.1 0.1
4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1
2 V to 6 V 3 10 10 10 pF
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C SN54HC377 SN74HC377
CC
MIN MAX MIN MAX MIN MAX
2 V 0 5 0 3 0 4
f
clock
t
w
t
h
Clock frequency
Pulse duration, CLK high or low
D
p
CLKEN high or low
Hold time after CLK
CLKEN inactive or active, data
4.5 V
6 V 0 29 0 19 0 23
2 V 100 150 125
4.5 V
6 V 17 25 21
2 V 100 150 125
4.5 V 20 30 25
6 V 17 25 21
2 V 100 150 125
4.5 V 20 30 25
6 V 17 25 21
2 V 5 5 5
4.5 V 5 5 5
6 V 5 5 5
0 25 0 16 0 20
20 30 25
MHz
ns
ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54HC377, SN74HC377
PARAMETER
V
UNIT
OCTAL D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCLS307A – JANUARY 1996 – REVISED MA Y 1997
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
FROM TO
(INPUT) (OUTPUT)
f
max
t
pd
t
t
CLK Any
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance per flip-flop No load 30 pF
pd
Any
CC
2 V 5 11 3 4
4.5 V 25 54 16 20
6 V 29 64 19 23
2 V 56 160 240 200
4.5 V 15 32 48 40
6 V 12 27 41 34
2 V 38 75 110 95
4.5 V 8 15 22 19
6 V 6 13 19 16
TA = 25°C SN54HC377 SN74HC377
MIN TYP MAX MIN MAX MIN MAX
MHz
ns
ns
6
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PARAMETER MEASUREMENT INFORMATION
50%
Test
Point
CL = 50 pF
(see Note A)
t
h
50%50%
From Output
Under Test
LOAD CIRCUIT
Reference
Input
t
su
Data
Input
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
90% 90%
t
r
VOLTAGE WAVEFORMS
SN54HC377, SN74HC377
OCTAL D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCLS307A – JANUARY 1996 – REVISED MA Y 1997
V
0 V
V
0 V
CC
CC
V
CC
0 V
V
50%50%
OH
10%10%
V
OL
t
f
V
OH
90%90%
V
OL
t
r
High-Level
Pulse
Low-Level
Pulse
Input
V
CC
0 V
V
CC
10%10%
0 V
t
f
In-Phase
Output
Out-of-Phase
Output
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
t
t
PLH
PHL
50%
t
w
50%
VOLTAGE WAVEFORMS
PULSE DURATIONS
90% 90%
t
r
50% 50%
10% 10%
t
f
VOLTAGE WAVEFORMS
50%
t
50%
50%
t
PHL
PLH
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, f
D. The outputs are measured one at a time with one input transition per measurement.
E. t
PLH
and t
PHL
is measured when the input duty cycle is 50%.
max
are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
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