Texas Instruments JM38510-65602BRA, SN54HC374J, SN74HC374DBR, SN74HC374DW, SN74HC374DWR Datasheet
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SN54HC374, SN74HC374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS141C – DECEMBER 1982 – REVISED JUL Y 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Eight D-Type Flip-Flops in a Single Package
D
High-Current 3-State True Outputs Can
Drive up to 15 LSTTL Loads
D
Full Parallel Access for Loading
D
Package Options Include Plastic Shrink
Small-Outline (DB), Small-Outline (DW),
Thin Shrink Small-Outline (PW), and
Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) DIPs
description
These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight flip-flops of the ’HC374 devices are
edge-triggered D-type flip-flops. On the positive
transition of the clock (CLK) input, the Q outputs
are set to the logic levels that were set up at the
data (D) inputs.
An output-enable (OE
) input places the eight
outputs in either a normal logic state (high or low
logic levels) or the high-impedance state. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly . The high-impedance state and increased drive provide the capability to drive
bus lines without interface or pullup components.
OE
does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54HC374 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74HC374 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
OE CLK D
Q
L ↑ H H
L ↑ LL
LH or L X Q
0
H X X Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
3212019
910111213
4
5
6
7
8
18
17
16
15
14
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
1D1QOE
5Q
5D
V
8Q
4Q
GND
CLK
SN54HC374 . . . FK PACKAGE
(TOP VIEW)
CC
SN54HC374 ...J OR W PACKAGE
SN74HC374 . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54HC374, SN74HC374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS141C – DECEMBER 1982 – REVISED JUL Y 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
1D
3
1D
4
2D
7
3D
EN
1
1Q
2
2Q
5
3Q
6
8
4D
13
5D
14
6D
4Q
9
5Q
12
6Q
15
OE
17
7D
18
8D
11
CLK
7Q
16
8Q
19
C1
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OE
To Seven Other Channels
1
11
3
2
CLK
1D
C1
1D
1Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): DB package 115° C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
SN54HC374, SN74HC374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS141C – DECEMBER 1982 – REVISED JUL Y 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54HC374 SN74HC374
MIN NOM MAX MIN NOM MAX
UNIT
V
CC
Supply voltage 2 5 6 2 5 6 V
VCC = 2 V 1.5 1.5
V
IH
High-level input voltage
VCC = 4.5 V
3.15 3.15
V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
V
IL
Low-level input voltage
VCC = 4.5 V 0 1.35 0 1.35
V
VCC = 6 V 0 1.8 0 1.8
V
I
Input voltage 0 V
CC
0 V
CC
V
V
O
Output voltage 0 V
CC
0 V
CC
V
VCC = 2 V 0 1000 0 1000
t
t
Input transition (rise and fall) time
VCC = 4.5 V
0 500 0 500
ns
VCC = 6 V 0 400 0 400
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54HC374 SN74HC374
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA
4.5 V 4.4 4.499 4.4 4.4
V
OH
VI = VIH or V
IL
6 V 5.9 5.999 5.9 5.9
V
IOH = –6 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –7.8 mA 6 V 5.48 5.8 5.2 5.34
2 V 0.002 0.1 0.1 0.1
IOL = 20 µA
4.5 V 0.001 0.1 0.1 0.1
V
OL
VI = VIH or V
IL
6 V 0.001 0.1 0.1 0.1
V
IOL = 6 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 7.8 mA 6 V 0.15 0.26 0.4 0.33
I
I
VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
I
OZ
VO = VCC or 0 6 V ±0.01 ±0.5 ±10 ±5 µA
I
CC
VI = VCC or 0, IO = 0 6 V 8 160 80 µA
C
i
2 V to 6 V 3 10 10 10 pF
SN54HC374, SN74HC374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS141C – DECEMBER 1982 – REVISED JUL Y 1998
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C SN54HC374 SN74HC374
V
CC
MIN MAX MIN MAX MIN MAX
UNIT
2 V 6 4 5
f
clock
Clock frequency
4.5 V
30 20 24
MHz
6 V 35 24 28
2 V 80 120 100
t
w
Pulse duration, CLK high or low
4.5 V 16 24 20
ns
6 V 14 20 17
2 V 100 150 125
t
su
Setup time, data before CLK
↑
4.5 V 20 30 25
ns
6 V 17 25 21
2 V 10 13 12
t
h
Hold time, data after CLK
↑
4.5 V 5 5 5
ns
6 V 5 5 5
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
FROM TO
TA = 25°C SN54HC374 SN74HC374
PARAMETER
(INPUT) (OUTPUT)
V
CC
MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 6 12 4 5
f
max
4.5 V 30 60 20 24
MHz
6 V 35 70 24 28
2 V 63 180 270 225
t
pd
CLK Any Q
4.5 V 17 36 54 45
ns
6 V 15 31 46 38
2 V 60 150 225 190
t
en
OE Any Q
4.5 V 16 30 45 38
ns
6 V 14 26 38 32
2 V 36 150 225 190
t
dis
OE Any Q
4.5 V 17 30 45 38
ns
6 V 16 26 38 32
2 V 28 60 90 75
t
t
Any Q
4.5 V 8 12 18 15
ns
6 V 6 10 15 13
SN54HC374, SN74HC374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS141C – DECEMBER 1982 – REVISED JUL Y 1998
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
FROM TO
TA = 25°C SN54HC374 SN74HC374
PARAMETER
(INPUT) (OUTPUT)
V
CC
MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 6 12 5
f
max
4.5 V 30 60 24
MHz
6 V 35 70 28
2 V 80 230 345 290
t
pd
CLK Any Q
4.5 V 22 46 69 58
ns
6 V 19 39 58 49
2 V 70 200 300 250
t
en
OE Any Q
4.5 V 25 40 60 50
ns
6 V 22 34 51 43
2 V 45 210 315 265
t
t
Any Q
4.5 V 17 42 63 53
ns
6 V 13 36 53 45
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
pd
Power dissipation capacitance per flip-flop No load 100 pF
SN54HC374, SN74HC374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS141C – DECEMBER 1982 – REVISED JUL Y 1998
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
t
h
t
su
50%
50%50%
10%10%
90% 90%
V
CC
V
CC
0 V
0 V
t
r
t
f
Reference
Input
Data
Input
50%
High-Level
Pulse
50%
V
CC
0 V
50%
50%
V
CC
0 V
t
w
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%50%
10%10%
90% 90%
V
CC
V
OH
V
OL
0 V
t
r
t
f
Input
In-Phase
Output
50%
t
PLH
t
PHL
50% 50%
10% 10%
90%90%
V
OH
V
OL
t
r
t
f
t
PHL
t
PLH
Out-of-
Phase
Output
50%
10%
90%
V
CC
≈ V
CC
V
OL
0 V
Output
Control
(Low-Level
Enabling)
Output
Waveform 1
(See Note B)
50%
t
PZL
t
PLZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
V
OH
≈ 0 V
50%
50%
t
PZH
t
PHZ
Output
Waveform 2
(See Note B)
≈ V
CC
Test
Point
From Output
Under Test
R
L
V
CC
S1
S2
LOAD CIRCUIT
PARAMETER C
L
t
PZH
tpd or t
t
t
dis
t
en
t
PZL
t
PHZ
t
PLZ
1 kΩ
1 kΩ
50 pF
or
150 pF
50 pF
Open Closed
R
L
S1
Closed Open
S2
Open Closed
Closed Open
50 pF
or
150 pF
Open Open––
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. For clock inputs, f
max
is measured when the input duty cycle is 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. t
PLZ
and t
PHZ
are the same as t
dis
.
G. t
PZL
and t
PZH
are the same as ten.
H. t
PLH
and t
PHL
are the same as tpd.
C
L
(see Note A)
Figure 1. Load Circuit and Voltage Waveforms
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Copyright 1998, Texas Instruments Incorporated
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