Texas Instruments SN74HC373DBR, SN74HC373DW, SN74HC373DWR, SN74HC373N, SN74HC373NSR Datasheet
...
SOIC
DW
HC373
TSSOP
PW
HC373
D
Wide Operating Voltage Range of 2 V to 6 V
D
High-Current 3-State True Outputs Can
Drive Up To 15 LSTTL Loads
D
Low Power Consumption, 80-µA Max I
D
Typical t
pd
= 13 ns
CC
SN54HC373, SN74HC373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS140C – DECEMBER 1982 – REVISED DECEMBER 2002
D
±6-mA Output Drive at 5 V
D
Low Input Current of 1 µA Max
D
Eight High-Current Latches in a Single
Package
D
Full Parallel Access for Loading
SN54HC373 ...J OR W PACKAGE
SN74HC373 . . . DB, DW, N, NS, OR PW PACKAGE
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
(TOP VIEW)
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
V
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
CC
SN54HC373 ...FK PACKAGE
2D
2Q
3Q
3D
4D
(TOP VIEW)
1D1QOE
3212019
4
5
6
7
8
910111213
4Q
LE
V
5Q
CC
8Q
18
17
16
15
14
5D
GND
description/ordering information
These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight latches of the ’HC373 devices are transparent D-type latches. While the latch-enable (LE) input is
high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that
were set up at the D inputs.
8D
7D
7Q
6Q
6D
T
A
PDIP – N Tube SN74HC373N SN74HC373N
–
–40°C to 85°C
–55°C to 125°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SOP – NS Tape and reel SN74HC373NSR HC373
SSOP – DB Tape and reel SN74HC373DBR HC373
–
CDIP – J Tube SNJ54HC373J SNJ54HC373J
CFP – W Tube SNJ54HC373W SNJ54HC373W
LCCC – FK Tube SNJ54HC373FK SNJ54HC373FK
ORDERING INFORMA TION
PACKAGE
†
Tube SN74HC373DW
Tape and reel SN74HC373DWR
Tube SN74HC373PW
Tape and reel SN74HC373PWR
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54HC373, SN74HC373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS140C – DECEMBER 1982 – REVISED DECEMBER 2002
description/ordering information (continued)
An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or
the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE
does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are off.
FUNCTION TABLE
(each latch)
INPUTS
OE LE D
L H H H
L HL L
L LX Q
H X X Z
logic diagram (positive logic)
OUTPUT
Q
0
1
OE
11
LE
1D
3
To Seven Other Channels
C1
1D
2
1Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
(VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
PARAMETER
TEST CONDITIONS
V
UNIT
SN54HC373, SN74HC373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS140C – DECEMBER 1982 – REVISED DECEMBER 2002
recommended operating conditions (see Note 3)
SN54HC373 SN74HC373
MIN NOM MAX MIN NOM MAX
V
V
V
V
V
∆t/∆v Input transition rise/fall time
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2 5 6 2 5 6 V
CC
VCC = 2 V 1.5 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
VCC = 4.5 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0.5 0.5
VCC = 4.5 V
VCC = 6 V 1.8 1.8
VCC = 2 V 1000 1000
VCC = 4.5 V
VCC = 6 V 400 400
3.15 3.15
1.35 1.35
CC
CC
500 500
0 V
0 V
CC
CC
V
V
V
V
ns
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54HC373 SN74HC373
MIN TYP MAX MIN MAX MIN MAX
V
V
V
V
I
I
I
C
OH
OL
I
OZ
CC
i
CC
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA
VI = VIH or V
VI = VIH or V
VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
VO = VCC or 0 6 V ±0.01 ±0.5 ±10 ±5 µA
VI = VCC or 0, IO = 0 6 V 8 160 80 µA
IL
IOH = –6 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –7.8 mA 6 V 5.48 5.8 5.2 5.34
IOL = 20 µA
IL
IOL = 6 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 7.8 mA 6 V 0.15 0.26 0.4 0.33
4.5 V 4.4 4.499 4.4 4.4
6 V 5.9 5.999 5.9 5.9
2 V 0.002 0.1 0.1 0.1
4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1
2 V to 6 V 3 10 10 10 pF
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54HC373, SN74HC373
V
UNIT
↓
↓
PARAMETER
V
UNIT
t
ns
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS140C – DECEMBER 1982 – REVISED DECEMBER 2002
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C SN54HC373 SN74HC373
CC
MIN MAX MIN MAX MIN MAX
2 V 80 120 100
t
w
t
su
t
h
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
Pulse duration, LE high
Setup time, data before LE
Hold time, data after LE
FROM TO
(INPUT) (OUTPUT)
pd
t
en
t
dis
t
t
D Q
LE Any Q
OE Any Q
OE Any Q
Any Q
4.5 V
6 V 14 20 17
2 V 50 75 63
4.5 V 10 15 13
6 V 9 13 11
2 V 20 26 24
4.5 V 10 13 12
6 V 10 13 12
CC
MIN TYP MAX MIN MAX MIN MAX
2 V 58 150 225 190
4.5 V 15 30 45 38
6 V 13 26 38 32
2 V 73 175 265 220
4.5 V 18 35 53 44
6 V 15 30 45 38
2 V 65 150 225 190
4.5 V 17 30 45 38
6 V 14 26 38 32
2 V 50 150 225 190
4.5 V 15 30 45 38
6 V 13 26 38 32
2 V 28 60 90 75
4.5 V 8 12 18 15
6 V 6 10 15 13
16 24 20
TA = 25°C SN54HC373 SN74HC373
ns
ns
ns
ns
ns
ns
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
V
UNIT
t
ns
SN54HC373, SN74HC373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS140C – DECEMBER 1982 – REVISED DECEMBER 2002
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
FROM TO
(INPUT) (OUTPUT)
D Q
pd
LE Any Q
t
en
t
t
OE Any Q
Any Q
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance per latch No load 100 pF
pd
CC
2 V 82 200 300 250
4.5 V 22 40 60 50
6 V 19 34 51 43
2 V 100 225 335 285
4.5 V 24 45 67 57
6 V 20 38 57 48
2 V 90 200 300 250
4.5 V 23 40 60 50
6 V 19 34 51 43
2 V 45 210 315 265
4.5 V 17 42 63 53
6 V 13 36 53 45
TA = 25°C SN54HC373 SN74HC373
MIN TYP MAX MIN MAX MIN MAX
ns
ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
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