Texas Instruments SN54HC273J, SN74HC273DBLE, SN74HC273DBR, SN74HC273DW, SN74HC273DWR Datasheet
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SN54HC273, SN74HC273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS136B – DECEMBER 1982 – REVISED MA Y 1997
D
Contain Eight Flip-Flops With Single-Rail
Outputs
D
Direct Clear Input
D
Individual Data Input to Each Flip-Flop
D
Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators
D
Package Options Include Plastic
Small-Outline (DW), Thin Shrink
Small-Outline (PW), and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
description
These circuits are positive-edge-triggered D-type
flip-flops with a direct clear (CLR) input.
Information at the data (D) inputs meeting the
setup time requirements is transferred to the
Q outputs on the positive-going edge of the clock
(CLK) pulse. Clock triggering occurs at a
particular voltage level and is not directly related
to the transition time of the positive-going pulse.
When CLK is at either the high or low level, the
D input has no effect at the output.
The SN54HC273 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC273 is characterized for
operation from –40°C to 85 °C.
SN54HC273 ...J OR W PACKAGE
SN74HC273 ...DW, N, OR PW PACKAGE
SN54HC273 . . . FK PACKAGE
2D
2Q
3Q
3D
4D
(TOP VIEW)
1
CLR
2
1Q
3
1D
4
2D
5
2Q
6
3Q
7
3D
8
4D
9
4Q
GND
10
(TOP VIEW)
1D1QCLR
3212019
4
5
6
7
8
910111213
4Q
CLK
GND
20
19
18
17
16
15
14
13
12
11
V
5Q
CC
V
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
8Q
18
17
16
15
14
5D
CC
8D
7D
7Q
6Q
6D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
FUNCTION TABLE
(each flip-flop)
INPUTS
CLR CLK D
L X X L
H ↑ HH
H ↑ LL
H L X Q
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
OUTPUT
Q
0
Copyright 1997, Texas Instruments Incorporated
1
SN54HC273, SN74HC273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS136B – DECEMBER 1982 – REVISED MA Y 1997
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
1
CLR
11
CLK
3
1D
4
2D 2Q
7
3D
8
4D 4Q
13
5D 5Q
14
6D 6Q
17
7D 7Q
18
8D 8Q
R
C1
1D
logic diagram (positive logic)
CLK
1D
11
3
1D
C1
R
2D
3D
4
1D
C1
R
7
1D
C1
R
4D
5D
8
1D
C1
R
13
1D
R
C1
12
15
16
19
2
5
6
9
6D
14
1D
R
1Q
3Q
C1
7D
17
1D
R
C1
8D
18
1D
C1
R
1
CLR
2
1Q
2Q
5
3Q
logic diagram, each flip-flop (positive logic)
C
D
CLK(I)
R
TG
C
C
TG
C
C
C
6
4Q
9
TG
12
5Q
C
C
TG
15
6Q
C
C
7Q
16
19
8Q
Q
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
SN54HC273, SN74HC273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS136B – DECEMBER 1982 – REVISED MA Y 1997
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
†
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions
SN54HC273 SN74HC273
MIN NOM MAX MIN NOM MAX
V
V
V
V
V
t
t
T
Supply voltage 2 5 6 2 5 6 V
CC
VCC = 2 V 1.5 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
Input transition (rise and fall) time
Operating free-air temperature –55 125 –40 85 °C
A
VCC = 4.5 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
VCC = 4.5 V
VCC = 6 V 0 1.8 0 1.8
VCC = 2 V 0 1000 0 1000
VCC = 4.5 V
VCC = 6 V 0 400 0 400
3.15 3.15
0 1.35 0 1.35
CC
CC
0 500 0 500
0 V
0 V
CC
CC
V
V
V
V
ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
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