Texas Instruments SN54HC273J, SN74HC273DBLE, SN74HC273DBR, SN74HC273DW, SN74HC273DWR Datasheet

SN54HC273, SN74HC273

OCTAL D-TYPE FLIP-FLOPS

WITH CLEAR

SCLS136B – DECEMBER 1982 – REVISED MA Y 1997

D

Contain Eight Flip-Flops With Single-Rail
Outputs

D

Direct Clear Input

D

Individual Data Input to Each Flip-Flop

D

Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators

D

Package Options Include Plastic
Small-Outline (DW), Thin Shrink
Small-Outline (PW), and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs

description

These circuits are positive-edge-triggered D-type
flip-flops with a direct clear (CLR) input.

Information at the data (D) inputs meeting the
setup time requirements is transferred to the
Q outputs on the positive-going edge of the clock
(CLK) pulse. Clock triggering occurs at a
particular voltage level and is not directly related
to the transition time of the positive-going pulse.
When CLK is at either the high or low level, the
D input has no effect at the output.

The SN54HC273 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC273 is characterized for
operation from –40°C to 85 °C.

SN54HC273 ...J OR W PACKAGE

SN74HC273 ...DW, N, OR PW PACKAGE

SN54HC273 . . . FK PACKAGE

2D
2Q
3Q
3D
4D

(TOP VIEW)

1

CLR

2

1Q

3

1D

4

2D

5

2Q

6

3Q

7

3D

8

4D

9

4Q

GND

10

(TOP VIEW)

1D1QCLR

3212019

4
5
6
7
8

910111213

4Q

CLK

GND

20
19
18
17
16
15
14
13
12
11

V

5Q

CC

V
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK

8Q

18
17
16
15
14

5D

CC

8D
7D
7Q
6Q
6D

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

FUNCTION TABLE

(each flip-flop)

INPUTS

CLR CLK D

L X X L
H ↑ HH
H ↑ LL
H L X Q

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

OUTPUT

Q

0

Copyright  1997, Texas Instruments Incorporated

1

SN54HC273, SN74HC273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR

SCLS136B – DECEMBER 1982 – REVISED MA Y 1997

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

†

1

CLR

11

CLK

3

1D

4

2D 2Q

7

3D

8

4D 4Q

13

5D 5Q

14

6D 6Q

17

7D 7Q

18

8D 8Q

R

C1

1D

logic diagram (positive logic)

CLK

1D

11

3

1D

C1

R

2D

3D

4

1D

C1

R

7

1D

C1

R

4D

5D

8

1D

C1

R

13

1D

R

C1

12
15
16
19

2
5
6
9

6D

14

1D

R

1Q

3Q

C1

7D

17

1D

R

C1

8D

18

1D

C1

R

1

CLR

2

1Q

2Q

5

3Q

logic diagram, each flip-flop (positive logic)

C

D

CLK(I)

R

TG

C

C

TG

C
C

C

6

4Q

9

TG

12

5Q

C

C

TG

15

6Q

C

C

7Q

16

19

8Q

Q

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

SN54HC273, SN74HC273

OCTAL D-TYPE FLIP-FLOPS

WITH CLEAR

SCLS136B – DECEMBER 1982 – REVISED MA Y 1997

absolute maximum ratings over operating free-air temperature range

Supply voltage range, V

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

†

Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

(see Note 2): DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions

SN54HC273 SN74HC273

MIN NOM MAX MIN NOM MAX

V

V

V

V
V

t

t

T

Supply voltage 2 5 6 2 5 6 V

CC

VCC = 2 V 1.5 1.5

High-level input voltage

IH

Low-level input voltage

IL

Input voltage 0 V

I

Output voltage 0 V

O

Input transition (rise and fall) time

Operating free-air temperature –55 125 –40 85 °C

A

VCC = 4.5 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
VCC = 4.5 V
VCC = 6 V 0 1.8 0 1.8

VCC = 2 V 0 1000 0 1000
VCC = 4.5 V
VCC = 6 V 0 400 0 400

3.15 3.15

0 1.35 0 1.35

CC
CC

0 500 0 500

0 V
0 V

CC
CC

V

V

V
V

ns

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN54HC273, SN74HC273

PARAMETER

TEST CONDITIONS

V

UNIT

V

UNIT

twPulse duration

ns

tsuSetup time before CLK↑

ns

↑

OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR

SCLS136B – DECEMBER 1982 – REVISED MA Y 1997

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

TA = 25°C SN54HC273 SN74HC273

MIN TYP MAX MIN MAX MIN MAX

V

V

V

V

I
I
C

OH

OL

I
CC

CC

2 V 1.9 1.998 1.9 1.9

IOH = –20 µA

VI = VIH or V

VI = VIH or V

VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
VI = VCC or 0, IO = 0 6 V 8 160 80 µA

i

IL

IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –5.2 mA 6 V 5.48 5.8 5.2 5.34

IOL = 20 µA

IL

IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33

4.5 V 4.4 4.499 4.4 4.4
6 V 5.9 5.999 5.9 5.9

2 V 0.002 0.1 0.1 0.1

4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1

2 V to 6 V 3 10 10 10 pF

timing requirements over recommended operating free-air temperature range (unless otherwise
noted)

TA = 25°C SN54HC273 SN74HC273

CC

MIN MAX MIN MAX MIN MAX

2 V 0 5 0 4 0 4

f

clock

t

h

Clock frequency

p

Hold time, data after CLK

CLR low

CLK high or low

Data

CLR inactive

4.5 V
6 V 0 32 0 21 0 25
2 V 80 120 100

4.5 V 16 24 20
6 V 14 20 17
2 V 80 120 100

4.5 V 16 24 20
6 V 14 20 17
2 V 100 150 125

4.5 V 20 30 25
6 V 17 25 21
2 V 100 150 125

4.5 V 20 30 25
6 V 17 25 21
2 V 0 0 0

4.5 V 0 0 0
6 V 0 0 0

0 27 0 18 0 21

MHz

ns

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER

V

UNIT

SN54HC273, SN74HC273

OCTAL D-TYPE FLIP-FLOPS

WITH CLEAR

SCLS136B – DECEMBER 1982 – REVISED MA Y 1997

switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)

FROM TO

(INPUT) (OUTPUT)

f

max

t

PHL

t

pd

t

t

CLR Any

CLK Any

operating characteristics, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT

C

Power dissipation capacitance per flip-flop No load 35 pF

pd

Any

CC

2 V 5 11 4 4

4.5 V 27 50 18 21
6 V 32 60 21 25
2 V 55 160 240 200

4.5 V 15 32 48 40
6 V 12 27 41 34
2 V 56 160 240 200

4.5 V 15 32 48 40
6 V 13 27 41 34
2 V 38 75 110 95

4.5 V 8 15 22 19
6 V 6 13 19 16

TA = 25°C SN54HC273 SN74HC273

MIN TYP MAX MIN MAX MIN MAX

MHz

ns

ns

ns

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

SN54HC273, SN74HC273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR

SCLS136B – DECEMBER 1982 – REVISED MA Y 1997

PARAMETER MEASUREMENT INFORMATION

50%

Test
Point

CL = 50 pF
(see Note A)

t

h

50%50%

From Output

Under Test

LOAD CIRCUIT

Reference

Input

t

su

Data

Input

SETUP AND HOLD AND INPUT RISE AND FALL TIMES

90% 90%

t

r

VOLTAGE WAVEFORMS

V

0 V

V

0 V

CC

CC

V

CC

0 V

V

50%50%

OH

10%10%

V

OL

t

f

V

OH

90%90%

V

OL

t

r

High-Level

Pulse

Low-Level

Pulse

Input

V

CC

0 V

V

CC

10%10%

0 V

t

f

In-Phase

Output

Out-of-Phase

Output

PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

50%

t

t

PLH

PHL

50%

t

w

50%

VOLTAGE WAVEFORMS

PULSE DURATIONS

90% 90%

t

r

50% 50%

10% 10%

t

f

VOLTAGE WAVEFORMS

50%

50%

50%

t

PHL

t

PLH

NOTES: A. CL includes probe and test-fixture capacitance.

B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following

characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, f
D. The outputs are measured one at a time with one input transition per measurement.
E. t

PLH

and t

PHL

is measured when the input duty cycle is 50%.

max

are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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