SN54HC266, SN74HC266
QUADRUPLE 2-INPUT EXCLUSIVE-NOR GATES
WITH OPEN-DRAIN OUTPUTS
SCLS135C – DECEMBER 1982 – REVISED MA Y 1997
D
Package Options Include Plastic
Small-Outline (D) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
description
The ’HC266 are composed of four independent
2-input exclusive-NOR gates and feature
open-drain outputs. They perform the Boolean
function Y = A
The SN54HC266 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC266 is characterized for
operation from –40°C to 85°C.
logic symbol
⊗ B or Y = AB + AB in positive logic.
FUNCTION TABLE
INPUTS
A B
L L H
L HL
H LL
H H H
OUTPUT
Y
†
SN54HC266 ...J OR W PACKAGE
SN74HC266 . . . D OR N PACKAGE
SN54HC266 . . . FK PACKAGE
1Y
NC
2Y
NC
2A
NC – No internal connection
(TOP VIEW)
1A
1
1B
2
1Y
3
2Y
4
2A
5
6
2B
GND
7
(TOP VIEW)
1B1ANC
3212019
4
5
6
7
8
910111213
2B
GND
NC
14
13
12
11
10
9
8
V
3A
CC
V
4B
4A
4Y
3Y
3B
3A
4B
18
17
16
15
14
3B
CC
4A
NC
4Y
NC
3Y
1
1A
2
1B
5
2A
6
2B
8
3A
9
3B
12
4A
13
4B
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
=1
logic diagram, each gate (positive logic)
A
B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
3
1Y
4
2Y
10
3Y
11
4Y
Y
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54HC266, SN74HC266
UNIT
PARAMETER
TEST CONDITIONS
V
UNIT
QUADRUPLE 2-INPUT EXCLUSIVE-NOR GATES
WITH OPEN-DRAIN OUTPUTS
SCLS135C – DECEMBER 1982 – REVISED MA Y 1997
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
†
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions
SN54HC266 SN74HC266
MIN NOM MAX MIN NOM MAX
V
V
V
V
V
t
t
T
Supply voltage 2 5 6 2 5 6 V
CC
VCC = 2 V 1.5 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
Input transition (rise and fall) time
Operating free-air temperature –55 125 –40 85 °C
A
VCC = 4.5 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
VCC = 4.5 V
VCC = 6 V 0 1.8 0 1.8
VCC = 2 V 0 1000 0 1000
VCC = 4.5 V
VCC = 6 V 0 400 0 400
3.15 3.15
0 1.35 0 1.35
CC
CC
0 500 0 500
0 V
0 V
CC
CC
V
V
V
V
ns
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
2
I
OH
V
I
I
I
CC
C
OL
i
CC
VI = VIH or VIL, VO = V
VI = VIH or V
VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
VI = VCC or 0, IO = 0 6 V 2 40 20 µA
IL
CC
IOL = 20 µA
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6 V 0.01 0.5 10 5 µA
2 V 0.002 0.1 0.1 0.1
4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1
2 V to 6 V 3 10 10 10 pF
TA = 25°C SN54HC266 SN74HC266
MIN TYP MAX MIN MAX MIN MAX
V
PARAMETER
V
UNIT
SN54HC266, SN74HC266
QUADRUPLE 2-INPUT EXCLUSIVE-NOR GATES
WITH OPEN-DRAIN OUTPUTS
SCLS135C – DECEMBER 1982 – REVISED MA Y 1997
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
FROM TO
(INPUT) (OUTPUT)
t
PLH
t
PHL
t
t
A or B Y
A or B Y
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance per gate No load 35 pF
pd
CC
2 V 60 125 190 155
4.5 V 13 25 38 31
6 V 10 23 32 26
2 V 60 100 150 125
4.5 V 13 20 30 25
6 V 10 17 25 21
2 V 28 75 110 95
Y
4.5 V 8 15 22 19
6 V 6 13 19 16
TA = 25°C SN54HC266 SN74HC266
MIN TYP MAX MIN MAX MIN MAX
ns
ns
ns
PARAMETER MEASUREMENT INFORMATION
V
CC
RL = 1 kΩ
From Output
Under Test
LOAD CIRCUIT
Input
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
C. The outputs are measured one at a time with one input transition per measurement.
90% 90%
t
r
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
Test
Point
CL = 50 pF
(see Note A)
V
50%50%
CC
10%10%
0 V
t
f
Figure 1. Load Circuit and Voltage Waveforms
Input
In-Phase
Output
Out-of-Phase
Output
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
t
PLH
t
PHL
90%
50%
10% 10%
VOLTAGE WAVEFORMS
V
50%
t
PHL
90%
t
PLH
t
f
50%
CC
0 V
V
OH
10%10%
V
OL
t
f
V
OH
V
OL
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 1998, Texas Instruments Incorporated
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