Datasheet SN54HC259J, SN74HC259NSR, SN74HC259PWLE, SN74HC259PWR, SN74HC259D Datasheet (Texas Instruments)
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SN54HC259, SN74HC259
8-BIT ADDRESSABLE LATCHES
SCLS134B – DECEMBER 1982 – REVISED MA Y 1997
D
8-Bit Parallel-Out Storage Register
Performs Serial-to-Parallel Conversion With
Storage
D
Asynchronous Parallel Clear
D
Active-High Decoder
D
Enable Input Simplifies Expansion
D
Expandable for n-Bit Applications
D
Four Distinct Functional Modes
D
Package Options Include Plastic
Small-Outline (D), Thin Shrink
Small-Outline (PW), and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
description
These 8-bit addressable latches are designed for
general-purpose storage applications in digital
systems. Specific uses include working registers,
serial-holding registers, and active-high decoders
or demultiplexers. They are multifunctional
devices capable of storing single-line data in eight
addressable latches, and being a 1-of-8 decoder
or demultiplexer with active-high outputs.
Four distinct modes of operation are selectable by
controlling the clear (CLR
In the addressable-latch mode, data at the data-in
terminal is written into the addressed latch. The
addressed latch follows the data input with all
unaddressed latches remaining in their previous
states. In the memory mode, all latches remain in
their previous states and are unaffected by the
data or address inputs. T o eliminate the possibility
of entering erroneous data in the latches, G
should be held high (inactive) while the address
lines are changing. In the 1-of-8 decoding or
demultiplexing mode, the addressed output
follows the level of the D input with all other
outputs low. In the clear mode, all outputs are low
and unaffected by the address and data inputs.
) and enable (G) inputs.
SN54HC259 ...J OR W PACKAGE
SN74HC259 . . . D, N, OR PW PACKAGE
SN54HC259 . . . FK PACKAGE
S2
Q0
NC
Q1
Q2
NC – No internal connection
(TOP VIEW)
S0
1
S1
2
S2
3
Q0
4
Q1
5
Q2
6
Q3
7
GND
8
(TOP VIEW)
S1S0NC
3212019
4
5
6
7
8
910111213
Q3
GND
NC
16
15
14
13
12
11
10
9
CC
V
Q4
V
CC
CLR
G
D
Q7
Q6
Q5
Q4
CLR
18
17
16
15
14
Q5
G
D
NC
Q7
Q6
The SN54HC259 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HC259 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54HC259, SN74HC259
ADDRESSED
OTHER
FUNCTION
8-BIT ADDRESSABLE LATCHES
SCLS134B – DECEMBER 1982 – REVISED MA Y 1997
INPUTS
Function Tables
FUNCTION
OUTPUT OF
EACH
CLR G
H L D Q
H HQiOQ
L LD L 8-line demultiplexer
L H L L Clear
LATCH
LATCH SELECTION
SELECT INPUTS
S2 S1 S0
L L L 0
L LH 1
L HL 2
L HH 3
H LL 4
H LH 5
H HL 6
H H H 7
OUTPUT
iO
iO
ADDRESSED
Addressable latch
Memory
LATCH
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC259, SN74HC259
8-BIT ADDRESSABLE LATCHES
SCLS134B – DECEMBER 1982 – REVISED MA Y 1997
logic symbol
†
S0
S1
S2
CLR
1
2
3
14
G
13
D
15
0
2
G8
Z9
Z10
9, 0D
10, 0R
9, 1D
10, 1R
9, 2D
10, 2R
9, 3D
10, 3R
9, 4D
10, 4R
9, 5D
10, 5R
9, 6D
10, 6R
9, 7D
10, 7R
8M
0
7
4
Q0
5
Q1
6
Q2
7
Q3
9
Q4
10
Q5
11
Q6
12
Q7
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, PW, and W packages.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54HC259, SN74HC259
8-BIT ADDRESSABLE LATCHES
SCLS134B – DECEMBER 1982 – REVISED MA Y 1997
logic diagram (positive logic)
S0
S1
S2
CLR
1
2
3
14
G
13
D
15
1D
C1
1
1D
C1
1
1D
C1
1
1D
C1
1
1D
C1
1
1D
C1
1
1D
C1
1
1D
C1
1
R
R
R
R
R
R
R
R
10
11
12
4
Q
0
5
Q
1
6
Q
2
7
Q
3
9
Q
4
Q
5
Q
6
Q
7
Pin numbers shown are for the D, J, N, PW, and W packages.
4
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logic symbol, each internal latch
SN54HC259, SN74HC259
8-BIT ADDRESSABLE LATCHES
SCLS134B – DECEMBER 1982 – REVISED MA Y 1997
D
C
R
1D
C1
1R
Q
logic diagram, each internal latch (positive logic)
C
D
C
R
absolute maximum ratings over operating free-air temperature range
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
(VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
stg
TG
C
C
C
C
TG
C
†
(see Note 2): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 149°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Q
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54HC259, SN74HC259
UNIT
PARAMETER
TEST CONDITIONS
V
UNIT
8-BIT ADDRESSABLE LATCHES
SCLS134B – DECEMBER 1982 – REVISED MA Y 1997
recommended operating conditions
V
V
V
V
V
t
t
T
Supply voltage 2 5 6 2 5 6 V
CC
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
Input transition (rise and fall) time
Operating free-air temperature –55 125 –40 85 °C
A
SN54HC259 SN74HC259
MIN NOM MAX MIN NOM MAX
VCC = 2 V 1.5 1.5
VCC = 4.5 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
VCC = 4.5 V
VCC = 6 V 0 1.8 0 1.8
VCC = 2 V 0 1000 0 1000
VCC = 4.5 V
VCC = 6 V 0 400 0 400
3.15 3.15
0 1.35 0 1.35
CC
CC
0 500 0 500
0 V
0 V
CC
CC
V
V
V
V
ns
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54HC259 SN74HC259
MIN TYP MAX MIN MAX MIN MAX
V
V
V
V
I
I
C
OH
OL
I
CC
CC
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA
VI = VIH or V
VI = VIH or V
VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
VI = VCC or 0, IO = 0 6 V 8 160 80 µA
i
IL
IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –5.2 mA 6 V 5.48 5.8 5.2 5.34
IOL = 20 µA
IL
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33
4.5 V 4.4 4.499 4.4 4.4
6 V 5.9 5.999 5.9 5.9
2 V 0.002 0.1 0.1 0.1
4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1
2 V to 6 V 3 10 10 10 pF
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
V
UNIT
twPulse duration
ns
↑
↑
PARAMETER
V
UNIT
SN54HC259, SN74HC259
8-BIT ADDRESSABLE LATCHES
SCLS134B – DECEMBER 1982 – REVISED MA Y 1997
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C SN54HC259 SN74HC259
CC
MIN MAX MIN MAX MIN MAX
2 V 80 120 100
CLR low
G low
t
su
t
h
Setup time, data or address before G
Hold time, data or address after G
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
FROM TO
(INPUT) (OUTPUT)
t
PHL
t
pd
t
t
CLR Any Q
Data Any Q
Address Any Q
G Any Q
Any
4.5 V 18 30 45 38
4.5 V 17 26 39 33
4.5 V 21 40 60 50
4.5 V 20 34 51 43
4.5 V 8 15 22 19
4.5 V 16 24 20
6 V 14 20 17
2 V 80 120 100
4.5 V 16 24 20
6 V 14 20 17
2 V 75 115 95
4.5 V 15 23 19
6 V 13 20 16
2 V 5 5 5
4.5 V 5 5 5
6 V 5 5 5
CC
2 V 60 150 225 190
6 V 14 26 38 32
2 V 56 130 195 165
6 V 13 22 33 28
2 V 74 200 300 250
6 V 17 34 51 43
2 V 66 170 255 215
6 V 16 29 43 37
2 V 28 75 110 95
6 V 6 13 19 16
TA = 25°C SN54HC259 SN74HC259
MIN TYP MAX MIN MAX MIN MAX
ns
ns
ns
ns
ns
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance per latch No load 33 pF
pd
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7
SN54HC259, SN74HC259
8-BIT ADDRESSABLE LATCHES
SCLS134B – DECEMBER 1982 – REVISED MA Y 1997
PARAMETER MEASUREMENT INFORMATION
50%
Test
Point
CL = 50 pF
(see Note A)
t
h
50%50%
From Output
Under Test
LOAD CIRCUIT
Reference
Input
t
su
Data
Input
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
90% 90%
t
r
VOLTAGE WAVEFORMS
V
0 V
V
0 V
CC
CC
V
CC
0 V
V
50%50%
OH
10%10%
V
OL
t
f
V
OH
90%90%
V
OL
t
r
High-Level
Pulse
Low-Level
Pulse
Input
V
CC
0 V
V
CC
10%10%
0 V
t
f
In-Phase
Output
Out-of-Phase
Output
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
t
t
PLH
PHL
50%
t
w
50%
VOLTAGE WAVEFORMS
PULSE DURATIONS
90% 90%
t
r
50% 50%
10% 10%
t
f
VOLTAGE WAVEFORMS
50%
50%
50%
t
PHL
t
PLH
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. t
PLH
and t
are the same as tpd.
PHL
Figure 1. Load Circuit and Voltage Waveforms
8
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