Texas Instruments SN54HC245J, SN74HC245PWLE, SN74HC245PWR, SN74HC245DBLE, SN74HC245DBR Datasheet

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OPERATION
SN54HC245, SN74HC245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCLS131B – DECEMBER 1982 – REVISED MA Y 1997
D
D
Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
description
These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.
The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE
) input can be used to disable the device so
that the buses are effectively isolated. The SN54HC245 is characterized for operation
over the full military temperature range of –55°C to 125°C. The SN74HC245 is characterized for operation from –40°C to 85°C.
SN54HC245 ...J OR W PACKAGE
SN74HC245 . . . DB, DW, N, OR PW PACKAGE
SN54HC245 . . . FK PACKAGE
A3 A4 A5 A6 A7
(TOP VIEW)
1
DIR
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
GND
10
(TOP VIEW)
A2A1DIR
3212019
4 5 6 7 8
910111213
20 19 18 17 16 15 14 13 12 11
CC
V
V OE B1 B2 B3 B4 B5 B6 B7 B8
OE
18 17 16 15 14
CC
B1 B2 B3 B4 B5
B7
B8
B6
A8
GND
FUNCTION TABLE
INPUTS
OE DIR
L L B data to A bus L H A data to B bus
H X Isolation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54HC245, SN74HC245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCLS131B – DECEMBER 1982 – REVISED MA Y 1997
logic symbol
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
OE
DIR
A1
A2 A3 A4 A5 A6 A7 A8
19 1
2
3 4 5 6 7 8 9
G3 3 EN1 [BA]
3 EN2 [AB]
1
2
logic diagram (positive logic)
1
DIR
18
17 16 15 14 13 12 11
B1
B2 B3 B4 B5 B6 B7 B8
A1
19
OE
2
18
B1
To Seven Other Channels
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
UNIT
SN54HC245, SN74HC245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCLS131B – DECEMBER 1982 – REVISED MA Y 1997
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions
SN54HC245 SN74HC245
MIN NOM MAX MIN NOM MAX
V
V
V
V V
t
t
T
Supply voltage 2 5 6 2 5 6 V
CC
VCC = 2 V 1.5 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
Input transition (rise and fall) time
Operating free-air temperature –55 125 –40 85 °C
A
VCC = 4.5 V VCC = 6 V 4.2 4.2 VCC = 2 V 0 0.5 0 0.5 VCC = 4.5 V VCC = 6 V 0 1.8 0 1.8
VCC = 2 V 0 1000 0 1000 VCC = 4.5 V VCC = 6 V 0 400 0 400
3.15 3.15
0 1.35 0 1.35
CC CC
0 500 0 500
0 V 0 V
CC CC
V
V
V V
ns
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3
SN54HC245, SN74HC245
PARAMETER
TEST CONDITIONS
V
UNIT
PARAMETER
V
UNIT
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCLS131B – DECEMBER 1982 – REVISED MA Y 1997
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
CC
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA
V
OH
V
OL
I
DIR or OE VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
I
I
A or B VO = VCC or 0 6 V ±0.01 ±0.5 ±10 ±5 µA
OZ
I
CC
C
DIR or OE 2 V to 6 V 3 10 10 10 pF
i
VI = VIH or V
VI = VIH or V
VI = VCC or 0, IO = 0 6 V 8 160 80 µA
IL
IOH = –6 mA 4.5 V 3.98 4.3 3.7 3.84 IOH = –7.8 mA 6 V 5.48 5.8 5.2 5.34
IOL = 20 µA
IL
IOL = 6 mA 4.5 V 0.17 0.26 0.4 0.33 IOL = 7.8 mA 6 V 0.15 0.26 0.4 0.33
4.5 V 4.4 4.499 4.4 4.4 6 V 5.9 5.999 5.9 5.9
2 V 0.002 0.1 0.1 0.1
4.5 V 0.001 0.1 0.1 0.1 6 V 0.001 0.1 0.1 0.1
TA = 25°C SN54HC245 SN74HC245
MIN TYP MAX MIN MAX MIN MAX
V
V
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
FROM TO
(INPUT) (OUTPUT)
t
pd
t
en
t
dis
t
t
A or B B or A
OE A or B
OE A or B
A or B
CC
2 V 40 105 160 130
4.5 V 15 21 32 26 6 V 12 18 27 22 2 V 125 230 340 290
4.5 V 23 46 68 58 6 V 20 39 58 49 2 V 74 200 300 250
4.5 V 25 40 60 50 6 V 21 34 51 43 2 V 20 60 90 75
4.5 V 8 12 18 15 6 V 6 10 15 13
TA = 25°C SN54HC245 SN74HC245
MIN TYP MAX MIN MAX MIN MAX
ns
ns
ns
ns
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER
V
UNIT
SN54HC245, SN74HC245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCLS131B – DECEMBER 1982 – REVISED MA Y 1997
switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1)
FROM TO
(INPUT) (OUTPUT)
t
pd
t
en
t
t
A or B B or A
OE A or B
A or B
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance per transceiver No load 40 pF
pd
CC
2 V 54 135 200 170
4.5 V 18 27 40 34 6 V 15 23 34 29 2 V 150 270 405 335
4.5 V 31 54 81 67 6 V 25 46 69 56 2 V 45 210 315 265
4.5 V 17 42 63 53 6 V 13 36 53 45
TA = 25°C SN54HC245 SN74HC245
MIN TYP MAX MIN MAX MIN MAX
ns
ns
ns
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
5
SN54HC245, SN74HC245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCLS131B – DECEMBER 1982 – REVISED MA Y 1997
PARAMETER MEASUREMENT INFORMATION
50%
t
PHL
t
PLH
S1
S2
50%50%
10%10%
Test
From Output
Under Test
(see Note A)
Input
In-Phase
Output
Out-of-Phase
Output
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
Input
50%
INPUT RISE AND FALL TIMES
Point
C
L
LOAD CIRCUIT
t
PLH
t
PHL
VOLTAGE WAVEFORMS
90% 90%
t
r
VOLTAGE WAVEFORM
R
L
90% 90%
t
r
50% 50%
10% 10%
t
f
V
CC
t
f
V
0 V
50%50%
CC
PARAMETER C
t
Output
Control
Output
Output
t
t
t
PZH
t
PZL
t
PHZ
t
PLZ
PZL
PZH
t
en
t
dis
tpd or t
V
CC
0 V
V
OH
10%10%
V
OL
t
f
V
90%90%
V
t
r
(Low-Level
OH
OL
Enabling)
Waveform 1
(See Note B)
Waveform 2
(See Note B)
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
R
L
1 k
1 k
50%
VOLTAGE WAVEFORMS
L
50 pF
or
150 pF
50 pF
50 pF
or
150 pF
V
50%
50%
CC
S1
Open Closed
Closed Open
Open Closed
Closed Open
Open Open––
50%
t
PLZ
10%
90%
t
PHZ
S2
V
CC
0 V
V
V
OL
V
OH
0 V
CC
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time with one input transition per measurement. E. t F. t
G. t
PLZ PZL PLH
and t and t and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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Copyright 1998, Texas Instruments Incorporated
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