SN54HC20, SN74HC20
DUAL 4-INPUT POSITIVE-NAND GATES
SCLS086D – DECEMBER 1982 – REVISED FEBRUARY 2000
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) DIPs
description
The ’HC20 devices contain two independent
4-input NAND gates. They perform the Boolean
function Y = A
positive logic.
The SN54HC20 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC20 is characterized for
operation from –40°C to 85°C.
A B C D
H H H H L
L XXX H
X LXX H
X XLX H
X X X L H
• B • C • D or Y = A + B + C + D in
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
SN54HC20 ...J OR W PACKAGE
SN74HC20 . . . D, DB, N, OR PW PACKAGE
SN54HC20 . . . FK PACKAGE
NC
NC
1C
NC
Y
1D
NC – No internal connection
(TOP VIEW)
1A
1
1B
2
NC
3
1C
4
1D
5
6
1Y
GND
7
(TOP VIEW)
1B1ANC
3212019
4
5
6
7
8
910111213
1Y
GND
NC
14
13
12
11
10
9
8
V
2Y
CC
V
2D
2C
NC
2B
2A
2Y
2D
18
17
16
15
14
2A
CC
2C
NC
NC
NC
2B
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
†
1
1A
2
1B
4
1C
5
1D
9
2A
10
2B
12
2C
13
2D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
&
6
1Y
8
2Y
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
SN54HC20, SN74HC20
UNIT
DUAL 4-INPUT POSITIVE-NAND GATES
SCLS086D – DECEMBER 1982 – REVISED FEBRUARY 2000
logic diagram (positive logic)
1
1A
2
1B
4
1C
5
1D
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
68
1Y
absolute maximum ratings over operating free-air temperature range
2A
2B
2C
2D
10
12
13
9
2Y
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
(VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54HC20 SN74HC20
MIN NOM MAX MIN NOM MAX
V
V
V
V
V
t
t
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2 5 6 2 5 6 V
CC
VCC = 2 V 1.5 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
Input transition (rise and fall) time
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
VCC = 4.5 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
VCC = 4.5 V
VCC = 6 V 0 1.8 0 1.8
VCC = 2 V 0 1000 0 1000
VCC = 4.5 V
VCC = 6 V 0 400 0 400
, literature number SCBA004.
3.15 3.15
0 1.35 0 1.35
CC
CC
0 500 0 500
0 V
0 V
CC
CC
V
V
V
V
ns
2
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PARAMETER
TEST CONDITIONS
V
UNIT
PARAMETER
V
UNIT
SN54HC20, SN74HC20
DUAL 4-INPUT POSITIVE-NAND GATES
SCLS086D – DECEMBER 1982 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54HC20 SN74HC20
MIN TYP MAX MIN MAX MIN MAX
V
V
V
V
I
I
C
OH
OL
I
CC
i
CC
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA
VI = VIH or V
VI = VIH or V
VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
VI = VCC or 0, IO = 0 6 V 2 40 20 µA
IL
IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –5.2 mA 6 V 5.48 5.8 5.2 5.34
IOL = 20 µA
IL
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33
4.5 V 4.4 4.499 4.4 4.4
6 V 5.9 5.999 5.9 5.9
2 V 0.002 0.1 0.1 0.1
4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1
2 V to 6 V 3 10 10 10 pF
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
FROM TO
(INPUT) (OUTPUT)
t
pd
t
t
A, B, C, or D Y
Y
CC
2 V 45 110 165 140
4.5 V 14 22 33 28
6 V 11 19 28 24
2 V 27 75 110 95
4.5 V 9 15 22 19
6 V 7 13 19 16
TA = 25°C SN54HC20 SN74HC20
MIN TYP MAX MIN MAX MIN MAX
ns
ns
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance No load 25 pF
pd
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3
SN54HC20, SN74HC20
DUAL 4-INPUT POSITIVE-NAND GATES
SCLS086D – DECEMBER 1982 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
Test
Point
CL = 50 pF
(see Note A)
V
50%50%
CC
10%10%
0 V
t
f
Input
From Output
Under Test
LOAD CIRCUIT
90% 90%
t
r
Input
In-Phase
Output
Out-of-Phase
Output
50%
t
t
PLH
PHL
50%
t
PHL
90% 90%
t
r
t
PLH
50% 50%
10% 10%
t
f
V
CC
0 V
V
50%50%
OH
10%10%
V
OL
t
f
V
OH
90%90%
V
OL
t
r
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. t
PLH
and t
are the same as tpd.
PHL
Figure 1. Load Circuit and Voltage Waveforms
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS
4
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