Texas Instruments SN54HC193J, SN74HC193D, SN74HC193DR, SN74HC193N, SN74HC193NSR Datasheet
...
SN54HC193, SN74HC193
4-BIT SYNCHRONOUS UP/DOWN COUNTERS
(DUAL CLOCK WITH CLEAR)
SCLS122B – DECEMBER 1982 – REVISED MA Y 1997
D
Look-Ahead Circuitry Enhances Cascaded
Counters
D
Fully Synchronous in Count Modes
D
Parallel Asynchronous Load for Modulo-N
Count Lengths
D
Asynchronous Clear
D
Package Options Include Plastic
Small-Outline (D) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
description
The ’HC193 are 4-bit synchronous, reversible,
up/down binary counters. Synchronous operation
is provided by having all flip-flops clocked
simultaneously so that the outputs change
coincidentally with each other when so instructed
by the steering logic. This mode of operation
eliminates the output counting spikes normally
associated with asynchronous (ripple-clock)
counters.
The outputs of the four flip-flops are triggered on
a low-to-high-level transition of either count
(clock) input (UP or DOWN). The direction of
counting is determined by which count input is
pulsed while the other count input is high.
SN54HC193 ...J OR W PACKAGE
SN74HC193 ...D OR N PACKAGE
DOWN
SN54HC193 . . . FK PACKAGE
Q
A
DOWN
NC
UP
Q
C
NC – No internal connection
(TOP VIEW)
B
1
Q
2
B
Q
3
A
4
5
UP
6
Q
C
7
Q
D
GND
8
(TOP VIEW)
B
QBNC
3212019
4
5
6
7
8
910111213
D
Q
GND
NC
16
15
14
13
12
11
10
9
V
D
CC
V
CC
A
CLR
BO
CO
LOAD
C
D
A
18
17
16
15
14
C
CLR
BO
NC
CO
LOAD
All four counters are fully programmable; that is, each output may be preset to either level by placing a low on
the load (LOAD
) input and entering the desired data at the data inputs. The output changes to agree with the
data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers
by simply modifying the count length with the preset inputs.
A clear (CLR) input has been provided that forces all outputs to the low level when a high level is applied. The
clear function is independent of the count and LOAD
inputs.
These counters were designed to be cascaded without the need for external circuitry . The borrow (BO) output
produces a low-level pulse while the count is zero (all outputs low) and DOWN is low. Similarly, the carry (CO)
output produces a low-level pulse while the count is maximum (9 or 15) and UP is low. The counters can then
be easily cascaded by feeding BO and CO to DOWN and UP, respectively , of the succeeding counter.
The SN54HC193 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HC193 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1997, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54HC193, SN74HC193
4-BIT SYNCHRONOUS UP/DOWN COUNTERS
(DUAL CLOCK WITH CLEAR)
SCLS122B – DECEMBER 1982 – REVISED MA Y 1997
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
†
CLR
UP
DOWN
LOAD
14
5
4
11
15
A
1
B
10
C
9
D
CT=0
G1
G2
C3
3D
2+
1–
CTRDIV16
[1]
[2]
[4]
[8]
1CT=15
2
CT=0
12
13
CO
BO
3
Q
A
2
Q
B
6
Q
C
7
Q
D
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
14
CLR
5
UP
DOWN
LOAD
4
11
15
A
1
B
SN54HC193, SN74HC193
4-BIT SYNCHRONOUS UP/DOWN COUNTERS
(DUAL CLOCK WITH CLEAR)
SCLS122B – DECEMBER 1982 – REVISED MA Y 1997
12
CO
13
BO
S
R
3
S
C1
1D
R
Q
A
2
S
C1
1D
R
10
C
S
C1
1D
R
9
D
S
C1
1D
R
Q
B
6
Q
C
7
Q
D
Pin numbers shown are for the D, J, N, and W packages.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
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