Texas Instruments SN54HC191J, SN74HC191D, SN74HC191DR, SN74HC191N, SN74HC191N3 Datasheet
...
SN54HC191, SN74HC191
4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121B – DECEMBER 1982 – REVISED MA Y 1997
D
Single Down/Up Count-Control Line
D
Look-Ahead Circuitry Enhances Speed of
Cascaded Counters
D
Fully Synchronous in Count Modes
D
Asynchronously Presettable With Load
Control
D
Package Options Include Plastic
Small-Outline (D) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
description
The ’HC191 are 4-bit synchronous, reversible,
up/down binary counters. Synchronous counting
operation is provided by having all flip-flops
clocked simultaneously so that the outputs
change coincident with each other when
instructed by the steering logic. This mode of
operation eliminates the output counting spikes
normally associated with asynchronous (rippleclock) counters.
The outputs of the four flip-flops are triggered on
a low-to-high-level transition of the clock (CLK)
input if the count-enable (CTEN) input is low. A
high at CTEN inhibits counting. The direction of
the count is determined by the level of the
down/up (D/U
counts up, and when D/U is high, it counts down.
) input. When D/U is low, the counter
SN54HC191 ...J OR W PACKAGE
SN74HC191 . . . D OR N PACKAGE
CTEN
SN54HC191 . . . FK PACKAGE
Q
A
CTEN
NC
D/U
Q
C
NC – No internal connection
(TOP VIEW)
B
1
Q
2
B
Q
3
A
4
5
D/U
6
Q
C
7
Q
D
GND
8
(TOP VIEW)
B
QBNC
3212019
4
5
6
7
8
910111213
D
Q
GND
NC
16
15
14
13
12
11
10
9
CC
V
D
V
CC
A
CLK
RCO
MAX/MIN
LOAD
C
D
A
18
17
16
15
14
C
CLK
RCO
NC
MAX/MIN
LOAD
These counters feature a fully independent clock circuit. Change at the control (CTEN
and D/U) inputs that
modifies the operating mode have no effect on the contents of the counter until clocking occurs. The function
of the counter is dictated solely by the condition meeting the stable setup and hold times.
These counters are fully programmable; that is, each of the outputs can be preset to either level by placing a
low on the load (LOAD) input and entering the desired data at the data inputs. The output changes to agree with
the data inputs independently of the level of CLK. This feature allows the counters to be used as modulo-N
dividers by simply modifying the count length with the preset inputs.
Two outputs are available to perform the cascading function: ripple clock (RCO) and maximum/minimum
(MAX/MIN) count. MAX/MIN produces a high-level output pulse with a duration approximately equal to one
complete cycle of the clock while the count is zero (all outputs low) counting down, or maximum (9 or 15)
counting up. RCO
produces a low-level output pulse under those same conditions, but only while CLK is low.
The counters can be easily cascaded by feeding RCO to CTEN of the succeeding counter if parallel clocking
is used, or to CLK if parallel enabling is used. MAX/MIN can be used to accomplish look ahead for high-speed
operation.
The SN54HC191 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HC191 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1997, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54HC191, SN74HC191
4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121B – DECEMBER 1982 – REVISED MA Y 1997
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
†
CTEN
D/U
CLK
LOAD
4
5
14
11
15
A
1
B
10
C
9
D
G1
M2 [DOWN]
M3 [UP]
G4
C5
5D
CTRDIV16
2(CT=0) Z6
3(CT=15) Z6
1,2–/1,3+
6,1,4
[1]
[2]
[4]
[8]
12
13
3
2
6
7
MAX/MIN
RCO
Q
A
Q
B
Q
C
Q
D
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
SN54HC191, SN74HC191
4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121B – DECEMBER 1982 – REVISED MA Y 1997
12
MAX/MIN
CTEN
D/U
CLK
LOAD
4
13
5
14
11
15
A
1
B
10
C
S
C1
1D
R
S
C1
1D
R
RCO
3
Q
A
2
Q
B
9
D
Pin numbers shown are for the D, J, N, and W packages.
S
1D
R
S
1D
R
C1
C1
6
Q
C
7
Q
D
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3
SN54HC191, SN74HC191
4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121B – DECEMBER 1982 – REVISED MA Y 1997
typical load, count, and inhibit sequence
The following sequence is illustrated below:
1. Load (preset) to binary 13
2. Count up to 14, 15 (maximum), 0, 1, and 2
3. Inhibit
4. Count down to 1, 0 (minimum), 15, 14, and 13
LOAD
A
Data
Inputs
Data
Outputs
CLK
D/U
CTEN
Q
Q
Q
Q
MAX/MIN
RCO
B
C
D
A
B
C
D
13
14 15 0 1 2
2210151413
Count Up
Load
4
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Inhibit
Count Down
UNIT
‡
SN54HC191, SN74HC191
4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121B – DECEMBER 1982 – REVISED MA Y 1997
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
†
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions
SN54HC191 SN74HC191
MIN NOM MAX MIN NOM MAX
V
V
V
V
V
t
t
T
‡
If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally ,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
Supply voltage 2 5 6 2 5 6 V
CC
VCC = 2 V 1.5 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
Input transition (rise and fall) time
Operating free-air temperature –55 125 –40 85 °C
A
VCC = 4.5 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
VCC = 4.5 V
VCC = 6 V 0 1.8 0 1.8
VCC = 2 V 0 1000 0 1000
VCC = 4.5 V
VCC = 6 V 0 400 0 400
3.15 3.15
0 1.35 0 1.35
CC
CC
0 500 0 500
0 V
0 V
CC
CC
V
V
V
V
ns
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5
SN54HC191, SN74HC191
PARAMETER
TEST CONDITIONS
V
UNIT
4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121B – DECEMBER 1982 – REVISED MA Y 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54HC191 SN74HC191
MIN TYP MAX MIN MAX MIN MAX
V
V
V
V
I
I
C
OH
OL
I
CC
CC
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA
VI = VIH or V
VI = VIH or V
VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
VI = VCC or 0, IO = 0 6 V 8 160 80 µA
i
IL
IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –5.2 mA 6 V 5.48 5.8 5.2 5.34
IOL = 20 µA
IL
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33
4.5 V 4.4 4.499 4.4 4.4
6 V 5.9 5.999 5.9 5.9
2 V 0.002 0.1 0.1 0.1
4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1
2 V to 6 V 3 10 10 10 pF
6
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V
UNIT
twPulse duration
ns
↑
↑
tsuSetup time
ns
↑
↑
↑
↑
↑
SN54HC191, SN74HC191
4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121B – DECEMBER 1982 – REVISED MA Y 1997
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C SN54HC191 SN74HC191
CC
MIN MAX MIN MAX MIN MAX
2 V 0 4.2 0 2.8 0 3.3
f
clock
t
h
Clock frequency
LOAD low
CLK high or low
Data before LOAD
CTEN before CLK
p
D/U before CLK
LOAD inactive before CLK
Data after LOAD
Hold time CTEN after CLK
D/U after CLK
4.5 V
6 V 0 24 0 16 0 19
2 V 120 180 150
4.5 V 24 36 30
6 V 21 31 26
2 V 120 180 150
4.5 V 24 36 30
6 V 21 31 26
2 V 150 230 188
4.5 V 30 46 38
6 V 25 38 32
2 V 205 306 255
4.5 V 41 61 51
6 V 35 53 44
2 V 205 306 255
4.5 V 41 61 51
6 V 35 53 44
2 V 150 225 190
4.5 V 30 45 38
6 V 25 38 32
2 V 5 5 5
4.5 V 5 5 5
6 V 5 5 5
2 V 5 5 5
4.5 V 5 5 5
6 V 5 5 5
2 V 5 5 5
4.5 V 5 5 5
6 V 5 5 5
0 21 0 14 0 17
MHz
ns
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SN54HC191, SN74HC191
PARAMETER
V
UNIT
or Q
D
t
ns
D/U
4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121B – DECEMBER 1982 – REVISED MA Y 1997
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54HC191 SN74HC191
MIN TYP MAX MIN MAX MIN MAX
MHz
ns
f
max
pd
t
t
FROM TO
(INPUT) (OUTPUT)
LOAD Any Q
A, B, C, or D
CLK Any Q
CTEN RCO
QA, QB, QC,
RCO
MAX/MIN
RCO
MAX/MIN
Any
CC
2 V 4.2 8 2.8 3.3
4.5 V 21 42 14 17
6 V 24 48 16 19
2 V 130 264 396 330
4.5 V 40 53 79 66
6 V 33 45 67 56
2 V 135 240 360 300
4.5 V 36 48 72 60
6 V 30 41 61 51
2 V 58 120 180 150
4.5 V 17 24 36 30
6 V 14 21 31 26
2 V 107 192 288 240
4.5 V 31 38 58 48
6 V 26 32 49 41
2 V 123 252 378 315
4.5 V 39 50 76 63
6 V 32 43 65 54
2 V 102 228 342 285
4.5 V 29 46 68 57
6 V 24 38 59 49
2 V 86 192 288 240
4.5 V 24 38 58 48
6 V 20 32 49 41
2 V 50 132 198 165
4.5 V 15 26 40 33
6 V 13 23 34 28
2 V 38 75 110 95
4.5 V 8 15 22 19
6 V 6 13 19 16
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
8
Power dissipation capacitance No load 50 pF
pd
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PARAMETER MEASUREMENT INFORMATION
50%
Test
Point
CL = 50 pF
(see Note A)
t
h
50%50%
From Output
Under Test
LOAD CIRCUIT
Reference
Input
t
su
Data
Input
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
90% 90%
t
r
VOLTAGE WAVEFORMS
SN54HC191, SN74HC191
4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121B – DECEMBER 1982 – REVISED MA Y 1997
V
0 V
V
0 V
CC
CC
50%50%
90%90%
High-Level
Pulse
Low-Level
Pulse
Input
V
CC
0 V
V
CC
10%10%
0 V
t
f
In-Phase
Output
Out-of-Phase
Output
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
t
t
PLH
PHL
50%
t
w
50%
VOLTAGE WAVEFORMS
PULSE DURATIONS
90% 90%
t
r
50% 50%
10% 10%
t
f
VOLTAGE WAVEFORMS
50%
t
50%
50%
t
PHL
PLH
V
CC
0 V
V
OH
10%10%
V
OL
t
f
V
OH
V
OL
t
r
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, f
D. The outputs are measured one at a time with one input transition per measurement.
E. t
PLH
and t
PHL
is measured when the input duty cycle is 50%.
max
are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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9
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