Texas Instruments JM38510-65308BEA, JM38510-65308BFA, SN54HC175J, SN74HC175APWR, SN74HC175D Datasheet
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SN54HC175, SN74HC175
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS299A – JANUARY 1996 – REVISED MA Y 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Contain Four Flip-Flops With Double-Rail
Outputs
D
Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators
D
Package Options Include Plastic
Small-Outline (D), Thin Shrink
Small-Outline (PW), and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
description
These monolithic positive-edge-triggered D-type
flip-flops have a direct clear (CLR) input. The
’HC175 feature complementary outputs from
each flip-flop.
Information at the data (D) inputs meeting the
setup time requirements is transferred to the
outputs on the positive-going edge of the clock
(CLK) pulse. Clock triggering occurs at a
particular voltage level and is not directly related
to the transition time of the positive-going edge of
CLK. When CLK is at either the high or low level,
the D input has no effect at the output.
The SN54HC175 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC175 is characterized for
operation from –40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS OUTPUTS
CLR CLK D Q Q
L X X L H
H ↑ HHL
H ↑ LLH
H L X Q
0
Q
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54HC175 ...J OR W PACKAGE
SN74HC175 . . . D, N, OR PW PACKAGE
(TOP VIEW)
SN54HC175 . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
1Q
1Q
1D
2D
2Q
2Q
GND
V
CC
4Q
4Q
4D
3D
3Q
3Q
CLK
3212019
910111213
4
5
6
7
8
18
17
16
15
14
4Q
4D
NC
3D
3Q
1Q
1D
NC
2D
2Q
1Q
CLR
NC
CLK
3Q
4Q
2Q
GND
NC
V
CC
NC – No internal connection
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54HC175, SN74HC175
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS299A – JANUARY 1996 – REVISED MA Y 1997
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
CLR
1Q
2Q
R
1
9
CLK C1
1D
4
1D
3
1Q
2
5
2D
6
2Q
7
12
3D
11
3Q
10
13
4D
14
4Q
15
3Q
4Q
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, PW, and W packages.
logic diagram (positive logic)
1Q
9
1
C1
1D
CLR
CLK
1D
R
1Q
To Three Other Channels
4
2
3
Pin numbers shown are for the D, J, N, PW, and W packages.
absolute maximum ratings over operating free-air temperature range
‡
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 149°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
SN54HC175, SN74HC175
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS299A – JANUARY 1996 – REVISED MA Y 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
SN54HC175 SN74HC175
MIN NOM MAX MIN NOM MAX
UNIT
V
CC
Supply voltage 2 5 6 2 5 6 V
VCC = 2 V 1.5 1.5
V
IH
High-level input voltage
VCC = 4.5 V
3.15 3.15
V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
V
IL
Low-level input voltage
VCC = 4.5 V
0 1.35 0 1.35
V
VCC = 6 V 0 1.8 0 1.8
V
I
Input voltage 0 V
CC
0 V
CC
V
V
O
Output voltage 0 V
CC
0 V
CC
V
VCC = 2 V 0 1000 0 1000
t
t
Input transition (rise and fall) time
VCC = 4.5 V
0 500 0 500
ns
VCC = 6 V 0 400 0 400
T
A
Operating free-air temperature –55 125 –40 85 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54HC175 SN74HC175
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA
4.5 V 4.4 4.499 4.4 4.4
V
OH
VI = VIH or V
IL
6 V 5.9 5.999 5.9 5.9
V
IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –5.2 mA 6 V 5.48 5.8 5.2 5.34
2 V 0.002 0.1 0.1 0.1
IOL = 20 µA
4.5 V 0.001 0.1 0.1 0.1
V
OL
VI = VIH or V
IL
6 V 0.001 0.1 0.1 0.1
V
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33
I
I
VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
I
CC
VI = VCC or 0, IO = 0 6 V 8 160 80 µA
C
i
2 V to 6 V 3 10 10 10 pF
SN54HC175, SN74HC175
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS299A – JANUARY 1996 – REVISED MA Y 1997
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C SN54HC175 SN74HC175
V
CC
MIN MAX MIN MAX MIN MAX
UNIT
2 V 0 6 0 4.2 0 5
f
clock
Clock frequency
4.5 V
0 31 0 21 0 25
MHz
6 V 0 36 0 25 0 29
2 V 80 120 100
CLR low
4.5 V 16 24 20
6 V 14 20 17
twPulse duration
2 V 80 120 100
ns
CLK high or low
4.5 V 16 24 20
6 V 14 20 17
2 V 100 150 125
Data
4.5 V 20 30 25
p
6 V 17 25 21
tsuSetup time before CLK↑
2 V 100 150 125
ns
CLR inactive
4.5 V 20 30 25
6 V 17 25 21
2 V 0 0 0
t
h
Hold time, data after CLK
↑
4.5 V 0 0 0
ns
6 V 0 0 0
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
FROM TO
TA = 25°C SN54HC175 SN74HC175
PARAMETER
(INPUT) (OUTPUT)
V
CC
MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 6 12 4.2 5
f
max
4.5 V 31 50 21 25
MHz
6 V 36 60 25 29
2 V 52 150 255 190
CLR Any
4.5 V 15 30 45 38
6 V 13 26 38 32
t
pd
2 V 58 150 255 190
ns
CLK Any
4.5 V 16 30 45 38
6 V 13 26 38 32
2 V 38 75 110 90
t
t
Any
4.5 V 8 15 22 19
ns
6 V 6 13 19 16
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
pd
Power dissipation capacitance per flip-flop No load 30 pF
SN54HC175, SN74HC175
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS299A – JANUARY 1996 – REVISED MA Y 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
t
h
t
su
50%
50%50%
10%10%
90% 90%
V
CC
V
CC
0 V
0 V
t
r
t
f
Reference
Input
Data
Input
50%
High-Level
Pulse
50%
V
CC
0 V
50%
50%
V
CC
0 V
t
w
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%50%
10%10%
90% 90%
V
CC
V
OH
V
OL
0 V
t
r
t
f
Input
In-Phase
Output
50%
t
PLH
t
PHL
50% 50%
10% 10%
90%90%
V
OH
V
OL
t
r
t
f
t
PHL
t
PLH
Out-of-Phase
Output
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, f
max
is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. t
PLH
and t
PHL
are the same as tpd.
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Figure 1. Load Circuit and Voltage Waveforms
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Copyright 1998, Texas Instruments Incorporated
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