Texas Instruments SN54HC165J, SN74HC165PWLE, SN74HC165PWR, SN74HC165D, SN74HC165DR Datasheet
...
FUNCTION
D
Complementary Outputs
D
Direct Overriding Load (Data) Inputs
D
Gated Clock Inputs
D
Parallel-to-Serial Data Conversion
D
Package Options Include Plastic
Small-Outline (D), Thin Shrink
Small-Outline (PW), and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
description
SN54HC165, SN74HC165
8-BIT PARALLEL-LOAD SHIFT REGISTERS
SCLS116C – DECEMBER 1982 – REVISED MAY 1997
SN54HC165 ...J OR W PACKAGE
SN74HC165 . . . D, N, OR PW PACKAGE
SH/LD
CLK
Q
GND
(TOP VIEW)
1
2
E
3
F
4
G
5
H
6
7
H
8
16
15
14
13
12
11
10
9
V
CC
CLK INH
D
C
B
A
SER
Q
H
The ’HC165 are 8-bit parallel-load shift registers
that, when clocked, shift the data toward a serial
(Q
) output. Parallel-in access to each stage is
H
SN54HC165 . . . FK PACKAGE
(TOP VIEW)
provided by eight individual direct data (A–H)
inputs that are enabled by a low level at the
shift/load (SH/LD) input. The ’HC165 also feature
a clock-inhibit (CLK INH) function and a
complementary serial (Q
) output.
H
Clocking is accomplished by a low-to-high
transition of the clock (CLK) input while SH/LD
is
held high and CLK INH is held low. The functions
of CLK and CLK INH are interchangeable. Since
a low CLK and a low-to-high transition of CLK INH
also accomplish clocking, CLK INH should be
changed to the high level only while CLK is high.
Parallel loading is inhibited when SH/LD
is held
CLK
3212019
4
E
5
F
6
NC
7
G
8
H
910111213
H
Q
NC – No internal connection
SH/LD
NC
NC
GND
CC
V
CLK INH
18
17
16
15
14
H
Q
SER
D
C
NC
B
A
high. While SH/LD is low, the parallel inputs to the
register are enabled independently of the levels of
the CLK, CLK INH, or serial (SER) inputs.
The SN54HC165 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HC165 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
SH/LD
†
Shift = content of each internal register shifts
toward serial output QH. Data at SER is
shifted into the first register.
CLK CLK INH
L X X Parallel load
H H X No change
H X H No change
H L ↑ Shift
H ↑ L Shift
†
†
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54HC165, SN74HC165
8-BIT PARALLEL-LOAD SHIFT REGISTERS
SCLS116C – DECEMBER 1982 – REVISED MAY 1997
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
SRG8
C1 [LOAD]
≥1
C2/
2D
1D
1D
1D
SH/LD
CLK INH
CLK
SER
1
15
2
10
11
A
12
B
13
C
14
D
3
E
4
F
5
G
6
H
Pin numbers shown are for the D, J, N, PW, and W packages.
logic diagram (positive logic)
9
Q
H
7
Q
H
ABCDEFGH
11 12 13 14 3 4 5 6
S
1D
R
C1
S
1D
R
C1
SH/LD
CLK INH
CLK
SER
1
15
2
10
Pin numbers shown are for the D, J, N, PW, and W packages.
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
9
Q
H
7
Q
H
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical shift, load, and inhibit sequence
CLK
CLK INH
SN54HC165, SN74HC165
8-BIT PARALLEL-LOAD SHIFT REGISTERS
SCLS116C – DECEMBER 1982 – REVISED MAY 1997
Data
Inputs
SER
SH/LD
Q
L
A
B
C
D
E
F
G
H
H
H
L
H
L
H
L
H
H
H
H
H
L
H
L
H
L
L
Q
H
Inhibit Serial Shift
Load
L
absolute maximum ratings over operating free-air temperature range
L
H
L
H
L
H
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
(VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 149°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
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3
SN54HC165, SN74HC165
UNIT
†
PARAMETER
TEST CONDITIONS
V
UNIT
8-BIT PARALLEL-LOAD SHIFT REGISTERS
SCLS116C – DECEMBER 1982 – REVISED MAY 1997
recommended operating conditions
SN54HC165 SN74HC165
MIN NOM MAX MIN NOM MAX
V
V
V
V
V
t
t
T
†
If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally ,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
Supply voltage 2 5 6 2 5 6 V
CC
VCC = 2 V 1.5 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
Input transition (rise and fall) time
Operating free-air temperature –55 125 –40 85 °C
A
VCC = 4.5 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
VCC = 4.5 V
VCC = 6 V 0 1.8 0 1.8
VCC = 2 V 0 1000 0 1000
VCC = 4.5 V
VCC = 6 V 0 400 0 400
3.15 3.15
0 1.35 0 1.35
CC
CC
0 500 0 500
0 V
0 V
CC
CC
V
V
V
V
ns
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54HC165 SN74HC165
MIN TYP MAX MIN MAX MIN MAX
V
V
V
V
I
I
C
OH
OL
I
CC
CC
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA
VI = VIH or V
VI = VIH or V
VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
VI = VCC or 0, IO = 0 6 V 8 160 80 µA
i
IL
IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –5.2 mA 6 V 5.48 5.8 5.2 5.34
IOL = 20 µA
IL
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33
4.5 V 4.4 4.499 4.4 4.4
6 V 5.9 5.999 5.9 5.9
2 V 0.002 0.1 0.1 0.1
4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1
2 V to 6 V 3 10 10 10 pF
4
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V
UNIT
twPulse duration
ns
↑
↑
↑
↑
↓
↑
thHold time
ns
↓
SN54HC165, SN74HC165
8-BIT PARALLEL-LOAD SHIFT REGISTERS
SCLS116C – DECEMBER 1982 – REVISED MAY 1997
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C SN54HC165 SN74HC165
CC
MIN MAX MIN MAX MIN MAX
2 V 0 6 0 4.2 0 5
f
clock
t
su
Clock frequency
SH/LD low
CLK high or low
SH/LD high before CLK
SER before CLK
Setup time CLK INH low before CLK
CLK INH high before CLK
Data before SH/LD
SER data after CLK
PAR data after SH/LD
4.5 V
6 V 0 36 0 25 0 29
2 V 80 120 100
4.5 V 16 24 20
6 V 14 20 17
2 V 80 120 100
4.5 V 16 24 20
6 V 14 20 17
2 V 80 120 100
4.5 V 16 24 20
6 V 14 20 17
2 V 40 60 50
4.5 V 8 12 10
6 V 7 10 9
2 V 100 150 125
4.5 V 20 30 25
6 V 17 25 21
2 V 40 60 50
4.5 V 8 12 10
6 V 7 10 9
2 V 100 150 125
4.5 V 20 30 25
6 V 17 26 21
2 V 5 5 5
4.5 V 5 5 5
6 V 5 5 5
2 V 5 5 5
4.5 V 5 5 5
6 V 5 5 5
0 31 0 21 0 25
MHz
ns
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5
SN54HC165, SN74HC165
PARAMETER
V
UNIT
8-BIT PARALLEL-LOAD SHIFT REGISTERS
SCLS116C – DECEMBER 1982 – REVISED MAY 1997
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54HC165 SN74HC165
MIN TYP MAX MIN MAX MIN MAX
MHz
ns
ns
f
max
t
pd
t
t
FROM TO
(INPUT) (OUTPUT)
SH/LD QH or Q
CLK QH or Q
H QH or Q
Any
CC
2 V 6 13 4.2 5
4.5 V 31 50 21 25
6 V 36 62 25 29
2 V 80 150 225 190
H
H
H
4.5 V 20 30 45 38
6 V 16 26 38 32
2 V 75 150 225 190
4.5 V 15 30 45 38
6 V 13 26 38 32
2 V 75 150 225 190
4.5 V 15 30 45 38
6 V 13 26 38 32
2 V 38 75 110 95
4.5 V 8 15 22 19
6 V 6 13 19 16
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance No load 75 pF
pd
6
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PARAMETER MEASUREMENT INFORMATION
50%
Test
Point
CL = 50 pF
(see Note A)
t
h
50%50%
From Output
Under Test
LOAD CIRCUIT
Reference
Input
t
su
Data
Input
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
90% 90%
t
r
VOLTAGE WAVEFORMS
SN54HC165, SN74HC165
8-BIT PARALLEL-LOAD SHIFT REGISTERS
SCLS116C – DECEMBER 1982 – REVISED MAY 1997
V
0 V
V
0 V
CC
CC
V
CC
0 V
V
50%50%
OH
10%10%
V
OL
t
f
V
OH
90%90%
V
OL
t
r
High-Level
Pulse
Low-Level
Pulse
Input
V
CC
0 V
V
CC
10%10%
0 V
t
f
In-Phase
Output
Out-of-Phase
Output
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
t
t
PLH
PHL
50%
t
w
50%
VOLTAGE WAVEFORMS
PULSE DURATIONS
90% 90%
t
r
50% 50%
10% 10%
t
f
VOLTAGE WAVEFORMS
50%
t
50%
50%
t
PHL
PLH
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, f
D. The outputs are measured one at a time with one input transition per measurement.
E. t
PLH
and t
PHL
is measured when the input duty cycle is 50%.
max
are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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7
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