Texas Instruments SN54HC164J, SN74HC164N, SN74HC164N3, SN74HC164D, SN74HC164DR Datasheet
...
SN54HC164, SN74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS115B – DECEMBER 1982 – REVISED MAY 1997
D
AND-Gated (Enable/Disable) Serial Inputs
D
Fully Buffered Clock and Serial Inputs
D
Direct Clear
D
Package Options Include Plastic
Small-Outline (D) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
description
These 8-bit shift registers feature AND-gated
serial inputs and an asynchronous clear (CLR)
input. The gated serial (A and B) inputs permit
complete control over incoming data; a low at
either input inhibits entry of the new data and
resets the first flip-flop to the low level at the next
clock (CLK) pulse. A high-level input enables the
other input, which then determines the state of the
first flip-flop. Data at the serial inputs can be
changed while CLK is high or low, provided the
minimum setup time requirements are met.
Clocking occurs on the low-to-high-level transition
of CLK.
The SN54HC164 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC164 is characterized for
operation from –40°C to 85°C.
SN54HC164 ...J OR W PACKAGE
SN74HC164 ...D OR N PACKAGE
SN54HC164 . . . FK PACKAGE
Q
A
NC
Q
B
NC
Q
C
NC – No internal connection
(TOP VIEW)
A
1
B
2
Q
3
A
Q
4
B
Q
5
C
Q
6
D
GND
7
(TOP VIEW)
BANC
3212019
4
5
6
7
8
910111213
D
Q
GND
NC
14
13
12
11
10
9
8
CC
V
CLK
V
Q
Q
Q
Q
CLR
CLK
H
Q
18
17
16
15
14
CLR
CC
H
G
F
E
Q
NC
Q
NC
Q
G
F
E
CLR CLK A B Q
L X X X L L L
H LXXQA0Q
H ↑ HHHQ
H ↑ LXLQ
H ↑ X L L Q
QA0, QB0, QH0 = the level of QA, QB, or QH, respectively,
before the indicated steady-state input conditions were
established
QAn, QGn = the level of QA or QG before the most recent
↑ transition of CLK: indicates a 1-bit shift
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
FUNCTION TABLE
INPUTS
OUTPUTS
A
QB...Q
B0QH0
AnQGn
AnQGn
AnQGn
H
Copyright 1997, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54HC164, SN74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS115B – DECEMBER 1982 – REVISED MAY 1997
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
†
SRG8
R
C1/
&
1D
CLR
CLK
9
8
1
A
2
B
logic diagram (positive logic)
8
CLK
10
11
12
13
3
Q
A
4
Q
B
5
Q
C
6
Q
D
Q
E
Q
F
Q
G
Q
H
1
A
2
B
9
CLR
Pin numbers shown are for the D, J, N, and W packages.
1D
R
C1
C1
1D
R
3
Q
A
4
Q
B
1D
R
C1
C1
1D
R
5
Q
C
6
Q
C1
1D
R
10
D
Q
C1
1D
R
11
E
Q
C1
1D
R
12
F
Q
C1
1D
R
13
G
Q
H
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical clear, shift, and clear sequence
CLR
A
B
Serial InputsOutputs
CLK
Q
A
Q
B
Q
C
Q
D
Q
E
SN54HC164, SN74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS115B – DECEMBER 1982 – REVISED MAY 1997
Q
F
Q
G
Q
H
Clear Clear
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
†
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54HC164, SN74HC164
UNIT
†
PARAMETER
TEST CONDITIONS
V
UNIT
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS115B – DECEMBER 1982 – REVISED MAY 1997
recommended operating conditions
SN54HC164 SN74HC164
MIN NOM MAX MIN NOM MAX
V
V
V
V
V
t
t
T
†
If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally ,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
Supply voltage 2 5 6 2 5 6 V
CC
VCC = 2 V 1.5 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
Input transition (rise and fall) time
Operating free-air temperature –55 125 –40 85 °C
A
VCC = 4.5 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
VCC = 4.5 V
VCC = 6 V 0 1.8 0 1.8
VCC = 2 V 0 1000 0 1000
VCC = 4.5 V
VCC = 6 V 0 400 0 400
3.15 3.15
0 1.35 0 1.35
CC
CC
0 500 0 500
0 V
0 V
CC
CC
V
V
V
V
ns
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54HC164 SN74HC164
MIN TYP MAX MIN MAX MIN MAX
V
V
V
V
I
I
C
OH
OL
I
CC
CC
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA
VI = VIH or V
VI = VIH or V
VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
VI = VCC or 0, IO = 0 6 V 8 160 80 µA
i
IL
IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –5.2 mA 6 V 5.48 5.8 5.2 5.34
IOL = 20 µA
IL
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33
4.5 V 4.4 4.499 4.4 4.4
6 V 5.9 5.999 5.9 5.9
2 V 0.002 0.1 0.1 0.1
4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1
2 V to 6 V 3 10 10 10 pF
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
V
UNIT
twPulse duration
ns
tsuSetup time before CLK↑
ns
↑
PARAMETER
V
UNIT
ns
SN54HC164, SN74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS115B – DECEMBER 1982 – REVISED MAY 1997
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C SN54HC164 SN74HC164
MIN MAX MIN MAX MIN MAX
0 31 0 21 0 25
MHz
ns
f
clock
t
h
Clock frequency
p
Hold time, data after CLK
CLR low
CLK high or low
Data
CLR inactive
CC
2 V 0 6 0 4.2 0 5
4.5 V
6 V 0 36 0 25 0 28
2 V 100 150 125
4.5 V 20 30 25
6 V 17 25 21
2 V 80 120 100
4.5 V 16 24 20
6 V 14 20 18
2 V 100 150 125
4.5 V 20 30 25
6 V 17 25 21
2 V 100 150 125
4.5 V 20 30 25
6 V 17 25 21
2 V 5 5 5
4.5 V 5 5 5
6 V 5 5 5
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54HC164 SN74HC164
MIN TYP MAX MIN MAX MIN MAX
MHz
ns
f
max
t
PHL
t
pd
t
t
FROM TO
(INPUT) (OUTPUT)
CLR Any Q
CLK Any Q
CC
2 V 6 10 4.2 5
4.5 V 31 54 21 25
6 V 36 62 25 28
2 V 140 205 295 255
4.5 V 28 41 59 51
6 V 24 35 51 46
2 V 115 175 265 220
4.5 V 23 35 53 44
6 V 20 30 45 38
2 V 38 75 110 95
4.5 V 8 15 22 19
6 V 6 13 19 16
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance No load 135 pF
pd
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54HC164, SN74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS115B – DECEMBER 1982 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
50%
Test
Point
CL = 50 pF
(see Note A)
t
h
V
CC
0 V
V
50%50%
CC
10%10%
0 V
t
f
In-Phase
Output
Out-of-Phase
Output
From Output
Under Test
LOAD CIRCUIT
Reference
Input
t
su
Data
Input
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
90% 90%
t
r
VOLTAGE WAVEFORMS
V
0 V
V
0 V
CC
CC
50%50%
10%10%
t
90%90%
t
High-Level
Pulse
Low-Level
Pulse
Input
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
t
t
PLH
PHL
50%
t
w
50%
VOLTAGE WAVEFORMS
PULSE DURATIONS
90% 90%
t
r
50% 50%
10% 10%
t
f
VOLTAGE WAVEFORMS
50%
t
50%
50%
t
PHL
PLH
V
CC
0 V
V
OH
V
OL
f
V
OH
V
OL
r
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, f
D. The outputs are measured one at a time with one input transition per measurement.
E. t
PLH
and t
PHL
is measured when the input duty cycle is 50%.
max
are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICA TIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
Loading...