Texas Instruments SN74HC163D, SN74HC163DR, SN74HC163N, SN74HC163NSR, SNJ54HC163FK Datasheet
...
SN54HC163, SN74HC163
4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS298A – JANUARY 1996 – REVISED MA Y 1997
D
Internal Look-Ahead for Fast Counting
D
Carry Output for n-Bit Cascading
D
Synchronous Counting
D
Synchronously Programmable
D
Package Options Include Plastic
Small-Outline (D) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
description
These synchronous, presettable counters feature
an internal carry look-ahead for application in
high-speed counting designs. The ’HC163 are
4-bit binary counters. Synchronous operation is
provided by having all flip-flops clocked
simultaneously so that the outputs change
coincident with each other when instructed by the
count-enable (ENP, ENT) inputs and internal
gating. This mode of operation eliminates the
output counting spikes normally associated with
synchronous (ripple-clock) counters. A buffered
clock (CLK) input triggers the four flip-flops on the
rising (positive-going) edge of the clock
waveform.
These counters are fully programmable; that is,
they can be preset to any number between 0 and
9 or 15. As presetting is synchronous, setting up
a low level at the load input disables the counter
and causes the outputs to agree with the setup
data after the next clock pulse, regardless of the
levels of the enable inputs.
SN54HC163 ...J OR W PACKAGE
SN74HC163 . . . D OR N PACKAGE
SN54HC163 . . . FK PACKAGE
A
B
NC
C
D
NC – No internal connection
(TOP VIEW)
CLR
1
CLK
2
A
3
B
4
C
5
D
6
ENP
7
GND
8
(TOP VIEW)
CLK
3 2 1 20 19
4
5
6
7
8
910111213
ENP
CLR
GND
NC
NC
16
15
14
13
12
11
10
9
CC
V
LOAD
V
CC
RCO
Q
A
Q
B
Q
C
Q
D
ENT
LOAD
RCO
18
17
16
15
14
ENT
Q
Q
NC
Q
Q
A
B
C
D
The clear function for the ’HC163 is synchronous. A low level at the clear (CLR
) input sets all four of the flip-flop
outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This
synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum
count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear
the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function.
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15 with Q
high). This high-level overflow ripple-carry pulse
A
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54HC163, SN74HC163
4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS298A – JANUARY 1996 – REVISED MA Y 1997
description (continued)
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
The SN54HC163 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HC163 is characterized for operation from –40°C to 85°C.
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
†
CTRDIV16
5CT=0
M1
M2
G3
G4
C5/2,3,4+
1,5D
3CT=15
[1]
[2]
[4]
[8]
CLR
LOAD
ENT
ENP
CLK
1
9
10
7
2
3
A
4
B
5
C
6
D
15
14
13
12
11
RCO
Q
A
Q
B
Q
C
Q
D
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
SN54HC163, SN74HC163
4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS298A – JANUARY 1996 – REVISED MA Y 1997
LOAD
ENT
ENP
CLK
CLR
9
10
†
7
2
1
3
A
4
B
LD
†
CK
CK
R
LD
M1
G2
1
, 2T/1C3
G4
3D
4R
M1
G2
1
, 2T/1C3
G4
3D
4R
14
13
15
RCO
Q
A
Q
B
M1
G2
1
, 2T/1C3
5
C
6
D
†
For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown
on the logic diagram of the D/T flip-flops.
Pin numbers shown are for the D, J, N, and W packages.
G4
3D
4R
M1
G2
1
, 2T/1C3
G4
3D
4R
12
11
Q
C
Q
D
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54HC163, SN74HC163
4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS298A – JANUARY 1996 – REVISED MA Y 1997
logic symbol, each D/T flip-flop
M1LD (Load)
G2TE (Toggle Enable)
CK (Clock)
D
(Inverted Data)
(Inverted Reset)
R
1, 2T/1C3
G4
3D
4R
logic diagram, each D/T flip-flop (positive logic)
CK
LD
TE
†
LD
LD
D
R
TG
TG
†
TG
†
CK
TG
CK
Q (Output)
TG
†
CK
†
TG
CK
†
Q
†
The origins of LD
4
and CK are shown in the logic diagram of the overall device.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical clear, preset, count, and inhibit sequence
The following sequence is illustrated below:
1. Clear outputs to zero (synchronous)
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit
CLR
LOAD
A
SN54HC163, SN74HC163
4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS298A – JANUARY 1996 – REVISED MA Y 1997
Data
Inputs
Data
Outputs
CLK
ENP
ENT
Q
Q
Q
Q
RCO
B
C
D
A
B
C
D
Sync
Clear
12 13
Preset
14 15 0 1 2
Count Inhibit
Async
Clear
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
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