Texas Instruments JM38510-65802BFA, JM38510-65802BEA, JM38510-65802B2A, SN54HC138J, SN74HC138D Datasheet

SN54HC138, SN74HC138

3-LINE TO 8-LINE DECODERS/DEMUL TIPLEXERS

SCLS107C – DECEMBER 1982 – REVISED MA Y 1997

D

Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems

D

Incorporate Three Enable Inputs to Simplify
Cascading and/or Data Reception

D

Package Options Include Plastic
Small-Outline (D), Thin Shrink
Small-Outline (PW), and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs

description

The ’HC138 are designed to be used in
high-performance memory-decoding or data­routing applications requiring very short
propagation delay times. In high-performance
memory systems, these decoders can be used to
minimize the effects of system decoding. When
employed with high-speed memories utilizing a
fast enable circuit, the delay times of these
decoders and the enable time of the memory are
usually less than the typical access time of the
memory. This means that the effective system
delay introduced by the decoders is negligible.

The conditions at the binary-select inputs at the
three enable inputs select one of eight output
lines. Two active-low and one active-high enable
inputs reduce the need for external gates or
inverters when expanding. A 24-line decoder can
be implemented without external inverters and a
32-line decoder requires only one inverter. An
enable input can be used as a data input for
demultiplexing applications.

SN54HC138 ...J OR W PACKAGE

SN74HC138 . . . D, N, OR PW PACKAGE

SN54HC138 ...FK PACKAGE

C

G

2A

NC

G

2B

G1

NC – No internal connection

(TOP VIEW)

A

1

B

2

C

3

2A

G

4
5

G

2B

6

G1

7

Y7

GND

8

(TOP VIEW)

BANC

3212019

4
5
6
7
8

910111213

Y7

GND

NC

16
15
14
13
12
11
10

9

CC

V

Y6

V
Y0
Y1
Y2
Y3
Y4
Y5
Y6

Y0

18
17
16
15
14

Y5

CC

Y1
Y2
NC
Y3
Y4

The SN54HC138 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HC138 is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1997, Texas Instruments Incorporated

1

SN54HC138, SN74HC138

OUTPUTS

3-LINE TO 8-LINE DECODERS/DEMUL TIPLEXERS

SCLS107C – DECEMBER 1982 – REVISED MA Y 1997

FUNCTION TABLE

INPUTS

ENABLE SELECT

G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

X H X X X X H H H H H H H H
X XHXXXHHHHHHHH
L XXXXXHHHHHHHH
H LLLLLLHHHHHHH
H LLLLHHLHHHHHH
H LLLHLHHLHHHHH
H LLLHHHHHLHHHH
H LLHLLHHHHLHHH
H LLHLHHHHHHLHH
H LLHHLHHHHHHLH
H L L H H H H H H H H H H L

EN

†

15

0
1

2

3

4
5

6

7

14
13

12

11

10

Y0
Y1

Y2

Y3

Y4
Y5

9

Y6

7

Y7

A
B
C

G1

G2A

2B

G

1
2
3

6
4
5

logic symbols (alternatives)

1

A

2

B

3

C

6

G1

4

G2A

5

2B

G

†

These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, J, N, PW, and W packages.

BIN/OCT

1
2
4

&

DMUX

0

0

G

7

2

&

0
1

2

3
4

5
6

7

15
14

13

12

11
10

Y0
Y1

Y2
Y3

Y4
Y5

9

Y6

7

Y7

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

1

A

2

B

SN54HC138, SN74HC138

3-LINE TO 8-LINE DECODERS/DEMUL TIPLEXERS

SCLS107C – DECEMBER 1982 – REVISED MA Y 1997

15

Y0

14

Y1

13

Y2

3

C

6

G1

4

G2A

5

G2B

Pin numbers shown are for the D, J, N, PW, and W packages.

absolute maximum ratings over operating free-air temperature range

†

12

11

10

Y3

Y4

Y5

9

Y6

7

Y7

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through V
Package thermal impedance, θ

or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 2): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 149°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

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3

SN54HC138, SN74HC138

UNIT

PARAMETER

TEST CONDITIONS

V

UNIT

3-LINE TO 8-LINE DECODERS/DEMUL TIPLEXERS

SCLS107C – DECEMBER 1982 – REVISED MA Y 1997

recommended operating conditions

V

V

V

V
V

t

t

T

Supply voltage 2 5 6 2 5 6 V

CC

VCC = 2 V 1.5 1.5

High-level input voltage

IH

Low-level input voltage

IL

Input voltage 0 V

I

Output voltage 0 V

O

Input transition (rise and fall) time

Operating free-air temperature –55 125 –40 85 °C

A

VCC = 4.5 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
VCC = 4.5 V
VCC = 6 V 0 1.8 0 1.8

VCC = 2 V 0 1000 0 1000
VCC = 4.5 V
VCC = 6 V 0 400 0 400

SN54HC138 SN74HC138

MIN NOM MAX MIN NOM MAX

3.15 3.15

0 1.35 0 1.35

CC
CC

0 500 0 500

0 V
0 V

CC
CC

V

V

V
V

ns

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

TA = 25°C SN54HC138 SN74HC138

MIN TYP MAX MIN MAX MIN MAX

V

V

V

V

I
I
C

OH

OL

I
CC

CC

2 V 1.9 1.998 1.9 1.9

IOH = –20 µA

VI = VIH or V

VI = VIH or V

VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
VI = VCC or 0, IO = 0 6 V 8 160 80 µA

i

IL

IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –5.2 mA 6 V 5.48 5.8 5.2 5.34

IOL = 20 µA

IL

IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33

4.5 V 4.4 4.499 4.4 4.4
6 V 5.9 5.999 5.9 5.9

2 V 0.002 0.1 0.1 0.1

4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1

2 V to 6 V 3 10 10 10 pF

4

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PARAMETER

V

UNIT

t

ns

SN54HC138, SN74HC138

3-LINE TO 8-LINE DECODERS/DEMUL TIPLEXERS

SCLS107C – DECEMBER 1982 – REVISED MA Y 1997

switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)

FROM TO

(INPUT) (OUTPUT)

A, B, or C Any Y

pd

Enable Any Y

t

t

operating characteristics, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT

C

Power dissipation capacitance No load 85 pF

pd

Any

CC

2 V 67 180 270 225

4.5 V 18 36 54 45
6 V 15 31 46 38
2 V 66 155 235 195

4.5 V 18 31 47 39
6 V 15 26 40 33
2 V 38 75 110 95

4.5 V 8 15 22 19
6 V 6 13 19 16

TA = 25°C SN54HC138 SN74HC138

MIN TYP MAX MIN MAX MIN MAX

ns

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

LOAD CIRCUIT

Input

NOTES: A. CL includes probe and test-fixture capacitance.

90% 90%

t

r

VOLTAGE WAVEFORM

INPUT RISE AND FALL TIMES

B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following

characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. t

PLH

and t

PHL

Test
Point

CL = 50 pF
(see Note A)

50%50%

are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms

V

CC

10%10%

0 V

t

f

Input

In-Phase

Output

Out-of-Phase

Output

V

50%

t

PLH

90% 90%

t

PHL

50% 50%

10% 10%

PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

VOLTAGE WAVEFORMS

50%

t

PHL

50%50%

t

r

t

PLH

t

f

CC

0 V

V

OH

10%10%

V

OL

t

f

V

OH

90%90%

V

OL

t

r

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5

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Copyright  1998, Texas Instruments Incorporated