High-Current 3-State Outputs Interface
Directly With System Bus or Can Drive up
to 15 LSTTL Loads
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Ceramic Flat (W) Packages,
Ceramic Chip Carriers (FK), and Standard
Plastic (N) and Ceramic (J) DIPs
description
These quadruple bus buffer gates feature
independent line drivers with 3-state outputs.
Each output is disabled when the associated
output-enable (OE) input is low.
The SN54HC126 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC126 is characterized for
operation from –40°C to 85°C.
FUNCTION TABLE
(each buffer)
INPUTS
OEA
HHH
HLL
LXZ
OUTPUT
Y
SN54HC126 ...J OR W PACKAGE
SN74HC126 . . . D, DB, OR N PACKAGE
SN54HC126 . . . FK PACKAGE
1Y
NC
2OE
NC
2A
NC – No internal connection
(TOP VIEW)
1OE
1
1A
2
1Y
3
2OE
4
2A
5
6
2Y
GND
7
(TOP VIEW)
1A
3212019
4
5
6
7
8
910111213
2Y
1OE
GND
NC
NC
14
13
12
11
10
9
8
V
3Y
CC
V
CC
4OE
4A
4Y
3OE
3A
3Y
4OE
18
17
16
15
14
3A
4A
NC
4Y
NC
3OE
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, and W packages.
†
1
1OE
2
1A
4
2OE
5
2A
10
3OE
9
3A
13
4OE
12
4A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EN
3
1Y
6
2Y
8
3Y
11
4Y
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
SN54HC126, SN74HC126
UNIT
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS103C – MARCH 1984 – REVISED FEBRUARY 1999
logic diagram (positive logic)
1
1OE
2
1A1Y
4
2OE
5
2A2Y
Pin numbers shown are for the D, DB, J, N, and W packages.
3
6
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
FROMTO
(INPUT)(OUTPUT)
t
pd
t
en
t
dis
t
t
AY
OEY
OEY
Any
CC
2 V47120180150
4.5 V14243630
6 V11203126
2 V57120180150
4.5 V16243630
6 V12203126
2 V35120180150
4.5 V17243630
6 V15203126
2 V28609075
4.5 V8121815
6 V6101513
TA = 25°CSN54HC126SN74HC126
MINTYPMAXMINMAXMINMAX
ns
ns
ns
ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54HC126, SN74HC126
PARAMETER
V
UNIT
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS103C – MARCH 1984 – REVISED FEBRUARY 1999
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
FROMTO
(INPUT)(OUTPUT)
t
pd
t
en
t
t
AY
OEY
operating characteristics, TA = 25°C
PARAMETERTEST CONDITIONSTYPUNIT
C
Power dissipation capacitance per gateNo load45pF
pd
Any
CC
2 V67150225188
4.5 V19304538
6 V15253933
2 V100135202169
4.5 V20274036
6 V17233630
2 V45210315265
4.5 V17426353
6 V13365345
TA = 25°CSN54HC126SN74HC126
MINTYPMAXMINMAXMINMAX
ns
ns
ns
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50%
t
t
S1
S2
PHL
PLH
50%50%
10%10%
Test
From Output
Under Test
(see Note A)
Input
In-Phase
Output
Out-of-Phase
Output
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
Input
50%
INPUT RISE AND FALL TIMES
Point
C
L
LOAD CIRCUIT
t
PLH
t
PHL
VOLTAGE WAVEFORMS
90%90%
t
r
VOLTAGE WAVEFORM
R
L
90%90%
t
r
50%50%
10%10%
t
f
SN54HC126, SN74HC126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS103C – MARCH 1984 – REVISED FEBRUARY 1999
V
CC
t
f
V
0 V
50%50%
CC
V
CC
0 V
V
OH
10%10%
V
OL
t
f
V
OH
90%90%
V
OL
t
r
PARAMETERC
t
Output
Control
Output
Output
t
t
t
t
t
PZL
t
PZH
PZH
PZL
PHZ
PLZ
t
en
t
dis
tpd or t
Waveform 1
(See Note B)
Waveform 2
(See Note B)
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
R
L
1 kΩ
1 kΩ
50%
VOLTAGE WAVEFORMS
L
50 pF
or
150 pF
50 pF
50 pF
or
150 pF
50%
50%
S1
OpenClosed
ClosedOpen
OpenClosed
ClosedOpen
OpenOpen––
50%
t
PLZ
10%
90%
t
PHZ
S2
V
CC
0 V
≈ V
V
OL
V
OH
≈ 0 V
CC
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. t
F. t
G. t
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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