Datasheet SN54HC125J, SN74HC125D, SN74HC125DBLE, SN74HC125DBR, SN74HC125DR Datasheet (Texas Instruments)
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SN54HC125, SN74HC125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS104B – MARCH 1984 – REVISED MA Y 1997
D
High-Current 3-State Outputs Interface
Directly With System Bus or Can Drive up
to 15 LSTTL Loads
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Ceramic Flat (W) Packages,
Ceramic Chip Carriers (FK), and Standard
Plastic (N) and Ceramic (J) 300-mil DIPs
description
These quadruple bus buffer gates feature
independent line drivers with 3-state outputs.
Each output is disabled when the associated
output-enable (OE
The SN54HC125 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC125 is characterized for
operation from –40°C to 85°C.
) input is high.
FUNCTION TABLE
(each buffer)
INPUTS
OE A
L H H
L LL
H X Z
OUTPUT
Y
SN54HC125 ...J OR W PACKAGE
SN74HC125 . . . D, DB, OR N PACKAGE
SN54HC125 . . . FK PACKAGE
1Y
NC
2OE
NC
2A
NC – No internal connection
(TOP VIEW)
1OE
1
1A
2
1Y
3
2OE
4
2A
5
6
2Y
GND
7
(TOP VIEW)
1A
3212019
4
5
6
7
8
910111213
2Y
1OE
GND
NC
NC
14
13
12
11
10
9
8
V
3Y
CC
V
CC
4OE
4A
4Y
3OE
3A
3Y
4OE
18
17
16
15
14
3A
4A
NC
4Y
NC
3OE
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, and W packages.
†
1
1OE
2
1A
4
2OE
5
2A
10
3OE
9
3A
13
4OE
12
4A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EN
3
1Y
6
2Y
8
3Y
11
4Y
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54HC125, SN74HC125
UNIT
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS104B – MARCH 1984 – REVISED MA Y 1997
logic diagram (positive logic)
1
1OE
2
1A 1Y
4
2OE
5
2A 2Y
Pin numbers shown are for the D, DB, J, N, and W packages.
3
6
absolute maximum ratings over operating free-air temperature range
10
3OE
9
3A 3Y
13
4OE
12
4A 4Y
8
11
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
(VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DB package 158°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions
V
V
V
V
V
t
t
T
Supply voltage 2 5 6 2 5 6 V
CC
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
Input transition (rise and fall) time
Operating free-air temperature –55 125 –40 85 °C
A
SN54HC125 SN74HC125
MIN NOM MAX MIN NOM MAX
VCC = 2 V 1.5 1.5
VCC = 4.5 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
VCC = 4.5 V
VCC = 6 V 0 1.8 0 1.8
VCC = 2 V 0 1000 0 1000
VCC = 4.5 V
VCC = 6 V 0 400 0 400
3.15 3.15
0 1.35 0 1.35
CC
CC
0 500 0 500
0 V
0 V
CC
CC
V
V
V
V
ns
2
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PARAMETER
TEST CONDITIONS
V
UNIT
PARAMETER
V
UNIT
SN54HC125, SN74HC125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS104B – MARCH 1984 – REVISED MA Y 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54HC125 SN74HC125
MIN TYP MAX MIN MAX MIN MAX
V
V
V
V
I
I
I
C
I
OZ
CC
OH
OL
i
CC
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA
VI = VIH or V
VI = VIH or V
VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
VO = VCC or 0 6 V ±0.01 ±0.5 ±10 ±5 µA
VI = VCC or 0, IO = 0 6 V 8 160 80 µA
IL
IOH = –6 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –7.8 mA 6 V 5.48 5.8 5.2 5.34
IOL = 20 µA
IL
IOL = 6 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 7.8 mA 6 V 0.15 0.26 0.4 0.33
4.5 V 4.4 4.499 4.4 4.4
6 V 5.9 5.999 5.9 5.9
2 V 0.002 0.1 0.1 0.1
4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1
2 V to 6 V 3 10 10 10 pF
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
FROM TO
(INPUT) (OUTPUT)
t
pd
t
en
t
dis
t
t
A Y
OE Y
OE Y
Any
CC
2 V 48 120 150 150
4.5 V 14 24 36 30
6 V 11 20 25 26
2 V 53 120 180 150
4.5 V 14 24 36 30
6 V 11 20 31 26
2 V 30 120 180 150
4.5 V 15 24 36 30
6 V 14 20 31 26
2 V 28 60 90 75
4.5 V 8 12 18 15
6 V 6 10 15 13
TA = 25°C SN54HC125 SN74HC125
MIN TYP MAX MIN MAX MIN MAX
ns
ns
ns
ns
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3
SN54HC125, SN74HC125
PARAMETER
V
UNIT
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS104B – MARCH 1984 – REVISED MA Y 1997
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
FROM TO
(INPUT) (OUTPUT)
t
pd
t
en
t
t
A Y
OE Y
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance per gate No load 45 pF
pd
Any
CC
2 V 67 150 225 190
4.5 V 19 30 45 38
6 V 15 25 39 32
2 V 100 135 200 170
4.5 V 20 27 40 34
6 V 17 23 34 29
2 V 45 210 315 265
4.5 V 17 42 63 53
6 V 13 36 53 45
TA = 25°C SN54HC125 SN74HC125
MIN TYP MAX MIN MAX MIN MAX
ns
ns
ns
4
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PARAMETER MEASUREMENT INFORMATION
50%
t
t
S1
S2
PHL
PLH
50%50%
10%10%
Test
From Output
Under Test
(see Note A)
Input
In-Phase
Output
Out-of-Phase
Output
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
Input
50%
INPUT RISE AND FALL TIMES
Point
C
L
LOAD CIRCUIT
t
PLH
t
PHL
VOLTAGE WAVEFORMS
90% 90%
t
r
VOLTAGE WAVEFORM
R
L
90% 90%
t
r
50% 50%
10% 10%
t
f
SN54HC125, SN74HC125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS104B – MARCH 1984 – REVISED MA Y 1997
V
CC
t
f
V
0 V
50%50%
CC
PARAMETER C
t
Output
Control
Output
Output
t
t
t
PZH
t
PZL
t
PHZ
t
PLZ
PZL
PZH
t
en
t
dis
tpd or t
V
CC
0 V
V
OH
10%10%
V
OL
t
f
V
90%90%
V
t
r
(Low-Level
OH
OL
Enabling)
Waveform 1
(See Note B)
Waveform 2
(See Note B)
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
R
L
1 kΩ
1 kΩ
50%
VOLTAGE WAVEFORMS
L
50 pF
or
150 pF
50 pF
50 pF
or
150 pF
≈ V
50%
50%
CC
S1
Open Closed
Closed Open
Open Closed
Closed Open
Open Open––
50%
t
PLZ
10%
90%
t
PHZ
S2
V
CC
0 V
≈ V
V
OL
V
OH
≈ 0 V
CC
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. t
F. t
G. t
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
.
Figure 1. Load Circuit and Voltage Waveforms
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5
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