Texas Instruments JM38510-65305BEA, SN54HC112J, SN74HC112D, SN74HC112DR, SN74HC112N Datasheet
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SN54HC112, SN74HC112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS099C – DECEMBER 1982 – REVISED APRIL 1999
D
Package Options Include Plastic
Small-Outline (D) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J) DIPs
description
The ’HC1 12 devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the preset (PRE
resets the outputs regardless of the levels of the
other inputs. When PRE
(high), data at the J and K inputs meeting the
setup time requirements are transferred to the
outputs on the negative-going edge of the clock
(CLK) pulse. Clock triggering occurs at a voltage
level and is not directly related to the rise time of
CLK. Following the hold-time interval, data at the
J and K inputs may be changed without affecting
the levels at the outputs. These versatile flip-flops
perform as toggle flip-flops by tying J and K high.
The SN54HC112 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC112 is characterized for
operation from –40°C to 85°C.
) or clear (CLR) inputs sets or
and CLR are inactive
PRE CLR CLK J K Q Q
L H X X X H L
H LXXXLH
LLXXXH
HH↓LLQ
HH↓HLHL
HH↓LHLH
HH↓H H Toggle
H H H X X Q
†
This configuration is unstable; that is, it does not persist
when either PRE
SN54HC112 ...J OR W PACKAGE
SN74HC112 ...D OR N PACKAGE
1CLK
1PRE
GND
SN54HC112 . . . FK PACKAGE
1J
1PRE
NC
1Q
1Q
FUNCTION TABLE
INPUTS
or CLR returns to its inactive (high) level.
NC – No internal connection
OUTPUTS
†
H
Q
0
Q
0
(TOP VIEW)
1
1K
2
1J
3
4
5
1Q
6
1Q
7
2Q
8
(TOP VIEW)
1K
1CLK
NC
3212019
4
5
6
7
8
910111213
2Q
GND
†
0
0
NC
16
15
14
13
12
11
10
9
CC
2Q V
V
CC
1CLR
2CLR
2CLK
2K
2J
2PRE
2Q
1CLR
18
17
16
15
14
2PRE
2CLR
2CLK
NC
2K
2J
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
SN54HC112, SN74HC112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS099C – DECEMBER 1982 – REVISED APRIL 1999
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
†
1J
1K
2J
2K
4
3
1
2
15
10
11
13
12
14
S
1J
C1
1K
R
1PRE
1CLK
1CLR
2PRE
2CLK
2CLR
logic diagram, each flip-flop (positive logic)
PRE
J
C
5
1Q
6
1Q
9
2Q
7
2Q
C
CLK
CLR
TG
K
C
C
C
TG
C
C
TG
C
C
TG
C
Q
Q
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
‡
SN54HC112, SN74HC112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS099C – DECEMBER 1982 – REVISED APRIL 1999
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
(VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 2): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
†
N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54HC112 SN74HC112
MIN NOM MAX MIN NOM MAX
V
V
V
V
V
t
t
T
‡
If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally ,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2 5 6 2 5 6 V
CC
VCC = 2 V 1.5 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
Input transition (rise and fall) time
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
VCC = 4.5 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
VCC = 4.5 V
VCC = 6 V 0 1.8 0 1.8
VCC = 2 V 0 1000 0 1000
VCC = 4.5 V
VCC = 6 V 0 400 0 400
, literature number SCBA004.
3.15 3.15
0 1.35 0 1.35
CC
CC
0 500 0 500
0 V
0 V
CC
CC
V
V
V
V
ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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