SN54HC02, SN74HC02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS076B – DECEMBER 1982 – REVISED MA Y 1997
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These devices contain four independent 2-input
NOR gates. They perform the Boolean function
Y = A + B or Y = A • B in positive logic.
The SN54HC02 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC02 is characterized for
operation from –40°C to 85°C.
FUNCTION TABLE
(each gate)
logic symbol
INPUTS
A B
H X L
X HL
L L H
†
OUTPUT
Y
SN54HC02 ...J OR W PACKAGE
SN74HC02 . . . D, DB, N, OR PW PACKAGE
SN54HC02 . . . FK PACKAGE
1B
NC
2Y
NC
2A
NC – No internal connection
(TOP VIEW)
1Y
1
1A
2
1B
3
2Y
4
2A
5
6
2B
GND
7
(TOP VIEW)
1A1YNC
3212019
4
5
6
7
8
910111213
2B
GND
NC
14
13
12
11
10
9
8
V
3A
CC
V
4Y
4B
4A
3Y
3B
3A
4Y
18
17
16
15
14
3B
CC
4B
NC
4A
NC
3Y
2
1A
3
1B
5
2A
6
2B
8
3A
9
3B
11
4A
12
4B
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
≥1
logic diagram (positive logic)
A
B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
1Y
4
2Y
10
3Y
13
4Y
Y
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54HC02, SN74HC02
UNIT
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS076B – DECEMBER 1982 – REVISED MA Y 1997
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
†
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DB package 158°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 170°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions
SN54HC02 SN74HC02
MIN NOM MAX MIN NOM MAX
V
V
V
V
V
t
t
T
Supply voltage 2 5 6 2 5 6 V
CC
VCC = 2 V 1.5 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
Input transition (rise and fall) time
Operating free-air temperature –55 125 –40 85 °C
A
VCC = 4.5 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
VCC = 4.5 V
VCC = 6 V 0 1.8 0 1.8
VCC = 2 V 0 1000 0 1000
VCC = 4.5 V
VCC = 6 V 0 400 0 400
3.15 3.15
0 1.35 0 1.35
CC
CC
0 500 0 500
0 V
0 V
CC
CC
V
V
V
V
ns
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
TEST CONDITIONS
V
UNIT
PARAMETER
V
UNIT
SN54HC02, SN74HC02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS076B – DECEMBER 1982 – REVISED MA Y 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54HC02 SN74HC02
MIN TYP MAX MIN MAX MIN MAX
V
V
V
V
I
I
C
OH
OL
I
CC
i
CC
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA
VI = VIH or V
VI = VIH or V
VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
VI = VCC or 0, IO = 0 6 V 2 40 20 µA
IL
IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –5.2 mA 6 V 5.48 5.8 5.2 5.34
IOL = 20 µA
IL
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33
4.5 V 4.4 4.499 4.4 4.4
6 V 5.9 5.999 5.9 5.9
2 V 0.002 0.1 0.1 0.1
4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1
2 V to 6 V 3 10 10 10 pF
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
FROM TO
(INPUT) (OUTPUT)
t
pd
t
t
A or B Y
Y
CC
2 V 45 90 135 115
4.5 V 9 18 27 23
6 V 8 15 23 20
2 V 38 75 110 95
4.5 V 8 15 22 19
6 V 6 13 19 16
TA = 25°C SN54HC02 SN74HC02
MIN TYP MAX MIN MAX MIN MAX
ns
ns
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance per gate No load 22 pF
pd
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54HC02, SN74HC02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS076B – DECEMBER 1982 – REVISED MA Y 1997
PARAMETER MEASUREMENT INFORMATION
Test
Point
CL = 50 pF
(see Note A)
V
50%50%
CC
10%10%
0 V
t
f
Out-of-Phase
Input
From Output
Under Test
LOAD CIRCUIT
90% 90%
t
r
Input
In-Phase
Output
Output
50%
t
t
PLH
PHL
50%
t
PHL
90% 90%
t
r
t
PLH
50% 50%
10% 10%
t
f
V
CC
0 V
V
50%50%
OH
10%10%
V
OL
t
f
V
OH
90%90%
V
OL
t
r
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. t
PLH
and t
are the same as tpd.
PHL
Figure 1. Load Circuit and Voltage Waveforms
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 1998, Texas Instruments Incorporated
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